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参数资料
| 型号： | ADMC331 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: REC3-S_DRW(Z)/H4,H6 - Safety standards and approval: EN 60950 certified, rated for 250VAV (LVD test report)- Applied for Ul 1950 Component Recognised Certification- 3W DIP Package- 4kVDC & 6kVDC Isolation- Regulated Output- Continuous Short Circiut Protection Auto-Restarting |
| 中文描述： | 单芯片DSP的电机控制器 |
| 文件页数： | 23/36页 |
| 文件大小： | 248K |
| 代理商： | ADMC331 |
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ADMC331
–23–
REV. B
6.
7.
8.
9.
Controls the PWM single/double update mode.
Controls the ADC conversion time modes.
Controls the AUXPWM mode.
Contains a status register (SYSSTAT) that indicates the
state of the
PWMTRIP
, PWMPOL and
PWMSR
pins, the
watchdog timer and the PWM timer.
10. Performs a reset of the motor control peripherals and con-
trol registers following a hardware, software or watchdog
initiated reset.
DSP
CORE
SPORT1
DR1A
DR1B
TFS1
RFS1/
SROM
SCLK1
MODECTRL (5 . . . 4)
UARTEN
DR1SEL
DT1
DR1
TFS1
RFS1
SCLK1
FL1
ADMC331
DT1
Figure 15. Internal Multiplexing of SPORT1 Pins
SPORT1 Control
The ADMC331 uses SPORT1 as the default serial port for boot
loading and as the interface to the development environment.
There are two data receive pins, DR1A and DR1B, on the
ADMC331. This permits DR1A to be used as the data receive
pin when interfacing to serial ROM or E
2
PROM for boot load-
ing. Alternatively, if connecting through another external device
for either boot loading or interface to the development environ-
ment, the DR1B pin can be used. Both data receive pins are
multiplexed internally into the single data receive input of
SPORT1. Two control bits in the MODECTRL register control
the state of the SPORT1 pins by manipulating internal multi-
plexers in the ADMC331. The configuration of SPORT1 is
illustrated in Figure 15.
Bit 4 of the MODECTRL register (DR1SEL) selects between
the two data receive pins. Setting Bit 4 of MODECTRL con-
nects the DR1B pin to the internal data receive port DR1 of
SPORT1. Clearing Bit 4 connects DR1A to DR1.
Setting Bit 5 of the MODECTRL register (UARTEN) config-
ures the serial port for UART mode. In this mode, the DR1 and
RFS1 pins of the internal serial port are connected together.
Additionally, setting the UARTEN bit connects the FL1 flag of
the DSP to the external RFS1/
SROM
pin. In this mode, this pin
is intended to be used to reset the external serial ROM device.
The monitor code in ROM automatically configures the SPORT1
pins during the boot sequence. Initially, the DR1SEL bit is
cleared and the UARTEN bit is set so that the ADMC331 first
attempts to perform a reset of the external memory device using
the RFS1/
SROM
pin. This is accomplished by toggling the FL1
flag using the following code segment:
SROMRESET: SET FL1;
TOGGLE FL1;
TOGGLE FL1;
RTS;
If successful, data will be clocked from the external device in a
continuous stream. The start of the data stream is detected by
the serial port on the RFS1 pin, which is connected internally to
the DR1 pin in this mode. If the serial load is successful, code
is downloaded and execution begins at the start of user program
memory (address 0x0030). Following a SROM/E
2
PROM boot
load, SPORT1 could be configured for normal synchronous
serial mode by setting the DR1SEL pin to select the DR1B data
receive pin and by clearing the UARTEN bit to return to SPORT
mode.
Failing a SROM/E
2
PROM boot load, the ADMC331 monitor
automatically sets the DR1SEL bit to select the DR1B pin and
remains in UARTEN mode. The monitor code then waits for a
header byte that tells it with which of the other interfaces it is to
communicate. Obviously, if a debugger interface is required on
SPORT1, it is not possible to use SPORT1 as a general purpose
synchronous serial port. If such a serial port is required, it is
recommended that SPORT0 be used.
Flag Pins
The ADMC331 provides flag pins. The alternate configuration
of SPORT1 includes a Flag In (FI) and Flag Out (FO) pin.
This alternate configuration of SPORT1 is selected by Bit 10 of
the DSP system control register, SYSCNTL at data memory
address, 0x3FFF. In the alternate configuration, the DR1 pin
(either DR1A or DR1B depending on the state of the DR1SEL
bit) becomes the FI pin and the DT1 pin becomes the FO pin.
Additionally, RFS1 is configured as the
IRQ0
interrupt input
and TFS1 is configured as the
IRQ1
interrupt. The serial port
clock, SCLK1, is still available in the alternate configuration.
Following boot loading from a serial memory device, it is pos-
sible to reconfigure the SPORT1 to this alternate configuration.
However, if a debugger interface is used, this configuration is
not possible as the normal serial port pins are required for
debugger communications.
The ADMC331 also contains two software flags, FL1 and FL2.
These flags may be controlled in software and perform specific
functions on the ADMC331. The FL1 pin has already been
described and is used to perform a reset of the external memory
device via the RFS1/
SROM
pin. The FL2 flag is used specifi-
cally to perform a full peripheral reset of the chip (including the
watchdog timer). This is accomplished by toggling the FL2 flag
in software using the following code segment:
PRESET:
SET FL2:
TOGGLE FL2;
TOGGLE FL2;
RTS;
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