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参数资料
| 型号： | ADN2531ACPZ-R2 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | IC LASER DRIVER 11.3GBPS 16LFCSP |
| 标准包装： | 1 |
| 类型： | 激光二极管驱动器 |
| 数据速率： | 11.3Gbps |
| 通道数： | 1 |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 36mA |
| 电流 - 调制： | 80mA |
| 电流 - 偏置： | 100mA |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 16-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-VQ |
| 包装： | 标准包装 |
| 安装类型： | 表面贴装 |
| 其它名称： | ADN2531ACPZ-R2DKR |
V BSET =
I BIAS (mA) 40
ADN2531
LAYOUT GUIDELINES
Due to the high frequencies at which the ADN2531 operates,
care should be taken when designing the PCB layout to obtain
optimum performance. For example, use controlled impedance
transmission lines for high speed signal paths, and keep the
length of transmission lines as short as possible to reduce losses
and pattern-dependent jitter. In addition, the PCB layout must
be symmetrical, both on the DATAP and DATAN inputs and on
the IMODP and IMODN outputs, to ensure a balance between
the differential signals.
Furthermore, all VCC and GND pins must be connected to
solid copper planes by using low inductance connections. When
these connections are made through vias, multiple vias can be
connected in parallel to reduce the parasitic inductance. Each
GND pin must be locally decoupled to VCC with high quality
capacitors (see Figure 40). If proper decoupling cannot be
achieved using a single capacitor, use multiple capacitors in
parallel for each GND pin. A 20 μF tantalum capacitor must be
used as the general decoupling capacitor for the entire module.
For recommended PCB layouts, including those suitable for the
SFP+ and XFP modules, contact sales. For guidelines on the
surface-mount assembly of the ADN2531 , see the AN-772
DESIGN EXAMPLE
Assuming that the impedance of the TOSA is 12 ?, the forward
voltage of the laser at low current is V F = 1.5 V, I BIAS = 40 mA,
I MOD = 40 mA, and V CC = 3.3 V, this design example calculates
? The headroom for the IBIAS, IMODP, and IMODN pins.
? The typical voltage required at the BSET and MSET pins to
produce the desired bias and modulation currents.
? The I BIAS monitor accuracy over the I BIAS current range.
Headroom Calculations
To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
the voltage at the IBIAS pin can be written as
V IBIAS = V CC ? V F ? ( I BIAS × R TOSA ) ? V LA
where:
V CC is the supply voltage.
V F is the forward voltage across the laser at low current.
R TOSA is the resistance of the TOSA.
V LA is the dc voltage drop across L5, L6, L7, and L8.
For proper operation, the minimum voltage at the IBIAS pin
Data Sheet
Therefore, V IBIAS = 1.32 V > 0.6 V, which satisfies the requirement
The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by
V COMPLIANCE_MAX = V CC ? 0.75 ? 4.4 × I BIAS (A)
For this example,
V COMPLIANCE_MAX = V CC ? 0.75 ? 4.4 × 0.04 = 2.374 V
Therefore, V IBIAS = 1.32 V < 2.374 V, which satisfies the
requirement.
To calculate the headroom at the modulation current pins
(IMODP and IMODN), the voltage has a dc component equal
to V CC due to the ac-coupled configuration and a swing equal to
I MOD × 50 ? because R TOSA is less than 100 ?. For proper
operation of the ADN2531,thevoltageateachmodulation
output pin should be within the normal operation region shown
Assuming the dc voltage drop across L1, L2, L3, and L4 is 0 V
and I MOD is 40 mA, the minimum voltage at the modulation
output pins is equal to
V CC ? ( I MOD × 12)/2 = V CC ? 0.24 V
Therefore, V CC ? 0.24 > V CC ? 1.1 V, which satisfies the
requirement.
The maximum voltage at the modulation output pins is equal to
V CC + ( I MOD × 12)/2 = V CC + 0.24 V
Therefore, V CC + 0.24 < V CC + 1.1 V, which satisfies the
requirement.
Headroom calculations must be repeated for the minimum and
maximum values of the required I BIAS and I MOD ranges to ensure
proper device operation over all operating conditions.
BSET and MSET Pin Voltage Calculations
To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2531 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required I BIAS range can be calculated using the BSET voltage to
I BIAS gain specified in Table 1. Assuming that I BIAS = 40 mA and that
I BIAS /V BSET = 100 mA/V (which is the typical I BIAS /V BSET ratio), the
BSET voltage is given by
= = 0 . 4 V
100 mA/V 100
The BSET voltage range can be calculated using the required
I BIAS range and the minimum and maximum BSET voltage to
The voltage required at the MSET pin to produce the desired
modulation current can be calculated using
should be greater than 0.6 V, as specified by the minimum
V MSET =
I MOD
K
Assuming that the voltage drop across the 50 ? transmission lines
is negligible and that V LA = 0 V, V F = 1.5 V, and I BIAS = 40 mA,
where K is the MSET voltage to I MOD ratio.
V IBIAS = 3.3 ? 1.5 ? (0.04 × 12) = 1.32 V
Rev. A | Page 16 of 20
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