参数资料
| 型号： | ADN2805ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/16页 |
| 文件大小： | 0K |
| 描述： | IC CLK/DATA REC 1.25GBPS 32LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 输入： | CML |
| 输出： | LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.25GHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 托盘 |
ADN2805
Data Sheet
Rev. B | Page 14 of 16
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane is recommended. To
reduce series inductance, solder the VEE pins directly to the
ground plane. If the ground plane is an internal plane and
connections to the ground plane are made through vias, multiple
vias can be used in parallel to reduce the series inductance,
especially on Pin 23, which is the ground return for the output
buffers. Connect the exposed pad to the ground plane using
plugged vias to prevent solder from leaking through the vias
during reflow.
Use of a 22 μF electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 μF and 1 nF ceramic chip capacitors,
place them between the IC power supply VCC and VEE, as
close as possible to the ADN2805 VCC pins.
If connections to the supply and ground are made through vias,
the use of multiple vias in parallel helps to reduce series
inductance, especially on Pin 24, which supplies power to the
high speed CLKOUTP/CLKOUTN and DATAOUTP/
DATAOUTN output buffers. Refer to Figure 14 for the
recommended connections.
By using adjacent power supply and ground planes, excellent
high frequency decoupling can be realized by using close
spacing between the planes. This capacitance is given by
( )
pF
ε
88
.
0
A/d
C
r
PLANE =
where:
ε
r
is the dielectric constant of the PCB material.
A is the area of the overlap of power and ground planes (cm2).
d is the separation between planes (mm).
For FR-4, εr = 4.4 mm and 0.25 mm spacing, C ~15 pF/cm2.
50 TRANSMISSION LINES
DATAOUTP
DATAOUTN
CLKOUTP
CLKOUTN
0.1F
22F
1nF
0.1F
0.47F ±20%
>300M INSULATION RESISTANCE
1nF
0.1F
1nF
+
VCC
50
OPTICAL
TRANSCEIVER
MODULE
VCC
NC
C
I2C CONTROLLER
VCC
07
12
1-
0
14
1
VCC
2
VCC
3
VREF
4
NIN
5
PIN
6
NC
7
NC
8
VEE
24
VCC
23
VEE
22
NC
21
SDA
20
SCK
19
SADDR5
18
VCC
17
VEE
9
10
R
E
F
C
L
K
P
11
R
E
F
C
L
K
N
12
V
C
13
V
E
14
C
F
2
15
C
F
1
16
L
O
L
32
V
C
31
V
C
30
V
E
29
D
A
TA
O
U
T
P
28
D
A
TA
O
U
T
N
27
S
Q
U
E
L
C
H
26
C
L
K
O
U
T
P
25
C
L
K
O
U
T
N
EXPOSED PAD
TIED OFF TO
VEE PLANE
WITH VIAS
Figure 14. Typical Applications Circuit
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