参数资料
| 型号： | ADN2816ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/24页 |
| 文件大小： | 0K |
| 描述： | IC CLK/DATA REC 675MBPS 32-LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 输入： | CML |
| 输出： | LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 675MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 托盘 |
| 产品目录页面： | 788 (CN2011-ZH PDF) |
Data Sheet
ADN2816
Rev. C | Page 13 of 24
At medium jitter frequencies, the gain and tuning range of the
VCO are not large enough to track input jitter. In this case, the
VCO control voltage becomes large and saturates, and the VCO
frequency dwells at one extreme of its tuning range or at the
other. The size of the VCO tuning range, therefore, has only a
small effect on the jitter accommodation. The delay-locked loop
control voltage is now larger, and therefore the phase shifter
takes on the burden of tracking the input jitter. The phase
shifter range, in UI, can be seen as a broad plateau on the jitter
tolerance curve. The phase shifter has a minimum range of 2 UI
at all data rates.
The gain of the loop integrator is small for high jitter
frequencies; therefore, larger phase differences are needed to
make the loop control voltage large enough to tune the range of
the phase shifter. Large phase errors at high jitter frequencies
cannot be tolerated. In this region, the gain of the integrator
determines the jitter accommodation. Because the gain of the
loop integrator declines linearly with frequency, jitter accom-
modation is lower with higher jitter frequency. At the highest
frequencies, the loop gain is very small, and little tuning of the
phase shifter can be expected. In this case, jitter accommodation is
determined by the eye opening of the input data, the static
phase error, and the residual loop jitter generation. The jitter
accommodation is roughly 0.5 UI in this region. The corner
frequency between the declining slope and the flat region is
the closed loop bandwidth of the delay-locked loop, which is
roughly 1.0 MHz at 675 Mb/s.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADN2816ACPZ | 制造商:Analog Devices 功能描述:CLOCK & DATA RECOVERY, 160MHZ, 111mA, LF |
| ADN2816ACPZ-500RL7 | 功能描述:IC CLK/DATA REC 675MBPS 32-LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ADN2816ACPZ-RL7 | 功能描述:IC CLK/DATA REC 675MBPS 32-LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ADN2816XCPZ | 制造商:AD 制造商全称:Analog Devices 功能描述:Continuous Rate 12.3 Mb/s to 675 Mb/s Clock and Data Recovery IC |
| ADN2817 | 制造商:AD 制造商全称:Analog Devices 功能描述:Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery ICs |
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