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参数资料
| 型号： | ADN2819ACPZ-CML |
| 厂商： | Analog Devices Inc |
| 文件页数： | 24/24页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 48LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，STM |
| 输入： | CML |
| 输出： | CML |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.7GHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP |
| 包装： | 托盘 |
ADN2819
Rev. B | Page 9 of 24
DEFINITION OF TERMS
MAXIMUM, MINIMUM, AND TYPICAL
SPECIFICATIONS
Specifications for every parameter are derived from statistical
analyses of data taken on multiple devices from multiple wafer
lots. Typical specifications are the mean of the distribution of
the data for that parameter. If a parameter has a maximum (or a
minimum), that value is calculated by adding to (or subtracting
from) the mean six times the standard deviation of the
distribution. This procedure is intended to tolerate production
variations. If the mean shifts by 1.5 standard deviations, the
remaining 4.5 standard deviations still provide a failure rate of
only 3.4 parts per million. For all tested parameters, the test
limits are guardbanded to account for tester variation and
therefore guarantee that no device is shipped outside of data
sheet specifications.
INPUT SENSITIVITY AND INPUT OVERDRIVE
Sensitivity and overdrive specifications for the quantizer involve
offset voltage, gain, and noise. The relationship between the
logic output of the quantizer and the analog voltage input is
shown in Figure 8. For a sufficiently large positive input voltage,
the output is always Logic 1; similarly for negative inputs, the
output is always Logic 0. However, the transitions between
output Logic Levels 1 and 0 are not at precisely defined input
voltage levels, but occur over a range of input voltages. Within
this zone of confusion, the output may be either 1 or 0, or it may
even fail to attain a valid logic state. The width of this zone is
determined by the input voltage noise of the quantizer. The
center of the zone of confusion is the quantizer input offset
voltage. Input overdrive is the magnitude of signal required to
guarantee the correct logic level with 1 × 10–10 confidence level.
0
1
INPUT (V p-p)
OUTPUT
NOISE
SENSITIVITY
(2
× OVERDRIVE)
OFFSET
OVERDRIVE
02999-B
-008
Figure 8. Input Sensitivity and Input Overdrive
SINGLE-ENDED VS. DIFFERENTIAL
AC-coupling is typically used to drive the inputs to the
quantizer. The inputs are internally dc biased to a common-
mode potential of ~0.6 V. Driving the ADN2819 single-ended
and observing the quantizer input with an oscilloscope probe at
the point indicated in Figure 9 shows a binary signal with an
average value equal to the common-mode potential and
instantaneous values above and below the average value. It is
convenient to measure the peak-to-peak amplitude of this
signal and to call the minimum required value the quantizer
sensitivity. Referring to Figure 8, since both positive and
negative offsets need to be accommodated, the sensitivity is
twice the overdrive.
50
50
QUANTIZER
+
ADN2819
VREF
PIN
SCOPE
PROBE
VREF
10mV p-p
02999-B
-009
Figure 9. Single-Ended Sensitivity Measurement
50
50
QUANTIZER
+
ADN2819
VREF
NIN
PIN
SCOPE
PROBE
VREF
5mV p-p
02999-B
-010
Figure 10. Differential Sensitivity Measurement
Driving the ADN2819 differentially (see Figure 10), sensitivity
seems to improve by observing the quantizer input with an
oscilloscope probe. This is an illusion caused by the use of a
single-ended probe. A 5 mV p-p signal appears to drive the
ADN2819 quantizer. However, the single-ended probe measures
only half the signal. The true quantizer input signal is twice this
value since the other quantizer input is complementary to the
signal being observed.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADN2819ACPZ-CML1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2819ACPZ-CML-RL | 功能描述:IC CLOCK/DATA RECOVERY 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| ADN2819ACPZ-CML-RL1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2820 | 制造商:AD 制造商全称:Analog Devices 功能描述:10.7 Gbps, 3.3V, Low Noise, TIA with Average Power Moniter |
| ADN2820ACHIPS | 制造商:Analog Devices 功能描述: |
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