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参数资料
| 型号： | ADN2848ACPZ-32-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC LASER DRIVER 1.25GBPS 32LFCSP |
| 标准包装： | 1,500 |
| 类型： | 激光二极管驱动器（光纤） |
| 数据速率： | 1.25Gbps |
| 通道数： | 1 |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 50mA |
| 电流 - 调制： | 80mA |
| 电流 - 偏置： | 100mA |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
ADN2848
Example:
ADN2848
Data Sheet
I FAIL = 50 mA so I DEGRADE = 45 mA
DATAP
TO FLIP-FLOPS
I ASET =
I FAIL
100
=
50 mA
100
= 500 μA
DATAN
50?
50?
V REG
= 2 . 4 k Ω
R ASET * =
=
1 .2 V 1 . 2
I ASET 500 μA
*The smallest valid value for R ASET is 1.2 kΩ, because this corresponds to the
maximum I BIAS of 100 mA.
The laser degrade alarm, DEGRADE, is provided to give a
warning of imminent laser failure if the laser diode degrades
further or if environmental conditions such as increasing
temperature continue to stress the LD.
The laser fail alarm, FAIL, is activated when the transmitter can
R
R = 2.5k?, DATA
R = 3k?, CLK
400μA TYP
Figure 5. AC Coupling of Data Inputs
For input signals that exceed 500 mV p-p single-ended, it is
no longer be guaranteed to be SONET/SDH compliant. This
occurs when one of the following conditions arise:
R1
DATAP/CLKP
ADN2848
?
The ASET threshold is reached.
R2
R3
DATAN/CLKN
R IN
?
The ALS pin is set high. This shuts off the modulation
and bias currents to the LD, resulting in the MPD
NOTE THAT R IN = 100? = THE DIFFERENTIAL
INPUT IMPEDANCE OF THE ADN2848.
current dropping to zero. This gives closed-loop
feedback to the system that ALS has been enabled.
DEGRADE is raised only when the bias current exceeds 90% of
ASET current.
MONITOR CURRENTS
IBMON, IMMON, and IMPDMON are current controlled
current sources from V CC . They mirror the bias, modulation,
and MPD current for increased monitoring functionality. An
external resistor to GND gives a voltage proportional to the
current monitored.
If the monitoring function IMPDMON is not required, the
IMPD pin must be grounded and the monitor photodiode
output must be connected directly to the PSET pin.
DATA AND CLOCK INPUTS
Data and clock inputs are ac-coupled (10 nF capacitors
recommended) and terminated via a 100 ? internal resistor
between DATAP and DATAN and also between the CLKP and
CLKN pins. There is a high impedance circuit to set the
common-mode voltage, which is designed to allow for
maximum input voltage headroom over temperature. It is
necessary that ac coupling be used to eliminate the need for
matching between common-mode voltages.
Figure 6. Attenuation Circuit
CCBIAS
When the laser is used in ac-coupled mode, the CCBIAS pin
and the I BIAS pin are tied together (see Figure 9). In dc-coupled
mode, CCBIAS is tied to V CC .
I BIAS
To achieve optimum optical eye quality, a pull-up resistor R Z , as
shown in Figure 8 and Figure 9, is required. The recommended
R Z value is approximately 200 ? ~ 500 ?.
AUTOMATIC LASER SHUTDOWN
The ADN2848 ALS allows compliance to ITU-T-G958 (11/94),
section 9.7. When ALS is logic high, both the bias and the
modulation currents are turned off. Correct operation of ALS is
confirmed by the FAIL alarm being raised when ALS is
asserted. Note that this is the only time that DEGRADE is low
while FAIL is high.
ALARM INTERFACES
The FAIL and DEGRADE outputs have an internal 30 k? pull-
up resistor that is used to pull the digital high value to V CC .
However, the alarm output can be overdriven with an external
resistor, allowing alarm interfacing to non-V CC levels. Non-V CC
alarm output levels must be below the V CC used for the
ADN2848.
Rev. B | Page 8 of 12
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