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| 型号： | ADP1043ADC1-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 36/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ADP1043A DAUGHTERCARD |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | ADP1043A |
| 主要属性： | * |
| 次要属性： | * |
| 已供物品： | 板 |
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ADP1043A
Table 11. Register 0x03—Fault Register 4 and Register 0x07—Latched Fault Register 4 (1 = Fault, 0 = Normal Operation)
Bits
7
6
5
4
3
2
Name
Reserved
Modulation
Address
Light load mode
Reserved
ACSNS
R/W
R
R
R
R
R
R
Description
Reserved.
Modulation is at its minimum or maximum limit.
The ADD resistor is not correct.
The system is in light load mode.
Reserved.
The ac sense timing or amplitude is not correct. The ac sense
Register
0x2E
0x3B
Action
None
None
None
Programmable
comparator has not tripped for one switching cycle.
1
0
CRC fault
EEPROM unlocked
R
R
The EEPROM contents downloaded are incorrect.
The EEPROM is unlocked.
Immediate shutdown
None
Table 12. Register 0x08 to Register 0x0D—Fault Configuration Registers
Register Name
Fault Configuration Register 1
Fault Configuration Register 2
Fault Configuration Register 3
Fault Configuration Register 4
Fault Configuration Register 5
Fault Configuration Register 6
Address
0x08
0x09
0x0A
0x0B
0x0C
0x0D
Bits
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
Flag
CS1 fast OCP
CS1 accurate OCP
CS2 accurate OCP
Load OVP (VS2 or VS3)
Local OVP (VS1)
External flag input (FLAGIN)
OTP
UVP
Accurate OrFET reverse voltage
Voltage continuity
Share bus
ACSNS
Shutdown Debounce
2 ms
2 ms
100 ms
100 ms
100 ms
100 ms
100 ms
100 ms
1 ms or 100 ms
Register 0x08 to Register 0x0D allow the user to program the response when each flag is set.
Table 13. Register 0x08 to Register 0x0D—Fault Configuration Register Bit Descriptions
Bits
7
Name
Timing
R/W
R/W
Description
This bit specifies when the flag is set.
0 = after debounce.
1 = immediately.
6
Resolve issue
R/W
This bit specifies when the part is reenabled after the fault that triggered the flag has been resolved.
0 = reenable after the power supply reenable time set in Register 0x0E[1:0].
1 = remain disabled; power supply must be restarted to reenable.
[5:4]
3
2
[1:0]
Action
Timing
Resolve issue
Action
R/W
R/W
R/W
R/W
These bits specify the action that the part takes in response to the flag.
Bit 5
Bit 4
Action
0
0
Ignore flag completely
0
1
Disable SR1 and SR2
1
0
Disable OrFET
1
1
Disable power supply (disable all PWM outputs and OrFET GATE)
Same as Bit 7.
Same as Bit 6.
Same as Bits[5:4].
Rev. 0 | Page 36 of 72
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