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| 型号： | ADP1043ADC1-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 69/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ADP1043A DAUGHTERCARD |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | ADP1043A |
| 主要属性： | * |
| 次要属性： | * |
| 已供物品： | 板 |
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ADP1043A
Table 120. Register 0x49—OUTC Rising Edge Dead Time in Resonant Mode
Bits
[7:0]
Name
Δt 5 (rising edge dead
time of OUTC)
R/W
R/W
Description
This register sets Δt 5 , which is the difference between the rising edge of OUTC and the midpoint
of the switching cycle, t B . Each LSB corresponds to 5 ns of resolution. When the register value is
from 0x00 to 0x7F, the rising edge of OUTC is trailing t B . When the value is from 0x80 to 0xFF,
the rising edge of OUTC is leading t B .
Bit 7
0
0
…
0
1
…
1
Bit 6
0
0
…
1
0
…
1
Bit 5
0
0
…
1
0
…
1
Bit 4
0
0
…
1
0
…
1
Bit 3
0
0
…
1
0
…
1
Bit 2
0
0
…
1
0
…
1
Bit 1
0
0
…
1
0
…
1
Bit 0
0
1
…
1
0
…
1
Δt 5
0 ns
5 ns trailing
…
635 ns trailing
640 ns leading
…
5 ns leading
Table 121. Register 0x4A—Burst Mode Operation in Resonant Mode
Bits
[7:6]
[5:0]
Name
Burst mode enable
Burst mode offset
R/W
R/W
R/W
Description
These bits are used to enable or disable burst mode operation.
Bit 7
Bit 6
Burst Mode
0
0
Disabled
0
1
Enabled for normal operation, but disabled during soft start
1
0
Disabled
1
1
Enabled for normal operation and during soft start
These bits, along with the highest switching frequency limit, determine the threshold value for
Table 122. Register 0x4B—OUTC Fallin g Edge Dead Time in Resonant Mode
Bits
[7:0]
Name
Δt 6 (falling edge dead
time of OUTC)
R/W
R/W
Description
This register sets Δt 6 , which is the leading time of the falling edge of OUTC from the end of the
switching cycle, t C . Each LSB corresponds to 5 ns of resolution.
Bit 7
0
0
…
1
Bit 6
0
0
…
1
Bit 5
0
0
…
1
Bit 4
0
0
…
1
Bit 3
0
0
…
1
Bit 2
0
0
…
1
Bit 1
0
0
…
1
Bit 0
0
1
…
1
Δt 6 (ns)
0
5
…
1275
Table 123. Register 0x4D—OUTD Risin g Edge Dead Time in Resonant Mode
Bits
[7:0]
Name
Δt 7 (rising edge dead
time of OUTD)
R/W
R/W
Description
This register sets Δt 7 , which is the difference between the rising edge of OUTD and the mid-
point of the switching cycle, t B . Each LSB corresponds to 5 ns of resolution. When the register
value is from 0x00 to 0x7F, the rising edge of OUTD is trailing t B . When the value is from 0x80 to
0xFF, the rising edge of OUTD is leading t B .
Bit 7
0
0
…
0
1
…
1
Bit 6
0
0
…
1
0
…
1
Bit 5
0
0
…
1
0
…
1
Bit 4
0
0
…
1
0
…
1
Bit 3
0
0
…
1
0
…
1
Bit 2
0
0
…
1
0
…
1
Bit 1
0
0
…
1
0
…
1
Bit 0
0
1
…
1
0
…
1
Δt 7
0 ns
5 ns trailing
…
635 ns trailing
640 ns leading
…
5 ns leading
Rev. 0 | Page 69 of 72
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