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| 型号： | ADP1043ADC1-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 42/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ADP1043A DAUGHTERCARD |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | ADP1043A |
| 主要属性： | * |
| 次要属性： | * |
| 已供物品： | 板 |
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ADP1043A
Table 32. Register 0x24—CS2 Analog Offset Trim
Bits
7
Name
CS2 high side
R/W
R/W
Description
This bit is set high if high-side current sensing is used. This bit is set low if low-side current
sensing is used. This is Step 2 in the CS2 Offset Trim section.
6
Offset polarity
R/W
1 = negative offset is introduced.
0 = positive offset is introduced.
[5:0]
CS2 offset trim
R/W
This register calibrates the secondary side (CS2) current sense common-mode error. It calibrates
for errors in the resistor divider network. This is Step 3 in the CS2 Offset Trim section.
Table 33. Register 0x25—CS2 Digital Tri m
Bits
[7:0]
Name
CS2 digital trim
R/W
R/W
Description
This register contains the CS2 digital trim level. This value is used to calibrate the CS2 value
that is read in Register 0x18. This is Step 4 in the CS2 Offset Trim section.
Table 34. Register 0x26—CS2 Accurate OCP Limit
Bits
[7:0]
Name
CS2 accurate OCP
R/W
R/W
Description
This register sets the CS2 accurate OCP current level. This 8-bit number is compared to the CS2
value register (Register 0x18). When the CS2 value register is greater than the value in this
register, the CS2 accurate OCP flag is set. The maximum setting of this register is 254 (0xFE).
Setting this register to 255 (0xFF) is not allowed.
Table 35. Register 0x27—CS1 Fast OCP Setting
Bits
[7:6]
Name
CS1 fast OCP
debounce
R/W
R/W
Description
These bits set the CS1 fast OCP debounce value. This is the minimum time that the CS1 signal
must be constantly above the fast OCP limit before the PWM outputs are shut down. When
this happens, all PWM outputs are disabled for the remainder of the switching cycle.
Bit 7
0
0
1
1
Bit 6
0
1
0
1
Debounce (ns)
0
40
80
120
5
VS balance enable
R/W
Setting this bit enables volt-second balance for the main transformer (used for full-bridge
configurations). This value introduces extra modulation on the OUTB and OUTD modulating
waveforms to provide volt-second balance in both branches of the full bridge. For more
information, see the Volt-Second Balance section.
4
3
CS1 fast OCP bypass
Constant current
mode
R/W
R/W
Setting this bit to 1 means that the FLAGIN pin is used for CS1 fast OCP instead of the CS1 pin.
When this bit is set, constant current mode is enabled 10% below the CS2 accurate OCP limit.
1 = constant current mode enabled.
0 = constant current mode disabled.
2
[1:0]
VS balance leading
edge blanking
CS1 fast OCP timeout
R/W
R/W
Setting this bit means that the current spike at the beginning of each CS1 reading is ignored
by the volt-second balance circuit.
If the CS1 fast OCP comparator is set, all PWM outputs that are on during that time are
immediately disabled for the remainder of the switching cycle. The PWM outputs resume
normal operation at the beginning of the next switching cycle. These bits set the number
of consecutive switching cycles for the comparator before the CS1 fast OCP flag is set.
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Number of Switching Cycles
1
2
4
8
Rev. 0 | Page 42 of 72
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