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参数资料
| 型号： | ADP130AUJZ-1.5-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/20页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 1.5V .35A TSOT-23-5 |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 1.5V |
| 输入电压： | 最高 3.6V |
| 电压 - 压降（标准）： | 0.07V @ 350mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 350mA（最小值） |
| 电流 - 限制（最小）： | 400mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-5 细型，TSOT-23-5 |
| 供应商设备封装： | TSOT-23-5 |
| 包装： | 标准包装 |
| 其它名称： | ADP130AUJZ-1.5-R7DKR |
Data Sheet
ABSOLUTE MAXIMUM RATINGS
ADP130
Table 3.
Parameter
VIN to GND
VBIAS to GND
EN to GND
VOUT to GND
Storage Temperature Range
Operating Temperature Range
Operating Junction Temperature
Lead Temperature (Soldering, 10 sec)
Rating
?0.3 V to +3.6 V
?0.3 V to +6 V
?0.3 V to VBIAS
?0.3 V to VIN
?65°C to +150°C
?40°C to +125°C
125°C
300°C
The junction-to-ambient thermal resistance (θ JA ) of the package
is based on modeling and calculation using a four-layer board.
The junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ JA may vary, depending on
PCB material, layout, and environmental conditions. The specified
values of θ JA are based on a four-layer, 4 in × 3 in circuit board.
For details about board construction, refer to JEDEC JESD51-7.
Ψ JB is the junction-to-board thermal characterization parameter
with units of °C/W. Ψ JB of the package is based on modeling and
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply only individually, not in combi-
nation. The ADP130 may be damaged when junction temperature
limits are exceeded. Monitoring ambient temperature does not
guarantee that the junction temperature is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature
may need to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can exceed
the maximum limit as long as the junction temperature is within
calculation using a four-layer board. The JEDEC JESD51-12
document, Guidelines for Reporting and Using Package Thermal
Information , states that thermal characterization parameters are
not the same as thermal resistances. Ψ JB measures the component
power flowing through multiple thermal paths rather than a single
path, as in thermal resistance (θ JB ). Therefore, Ψ JB thermal paths
include convection from the top of the package as well as radiation
from the package, factors that make Ψ JB more useful in real world
applications. Maximum junction temperature (T J ) is calculated
from the board temperature (T B ) and power dissipation (P D ), using
the following formula:
T J = T B + ( P D × Ψ JB )
Refer to the JEDEC JESD51-8 and JESD51-12 documents for
more detailed information about Ψ JB .
THERMAL RESISTANCE
θ JA and Ψ JB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
specification limits. The junction temperature (T J ) of the device
is dependent on the ambient temperature (T A ), the power
dissipation of the device (P D ), and the junction-to-ambient thermal
resistance of the package (θ JA ). T J is calculated using the
Table 4. Thermal Resistance
Package Type θ JA
5-Lead TSOT 170
Ψ JB
43
Unit
°C/W
following formula:
T J = T A + ( P D × θ JA )
ESD CAUTION
Rev. C | Page 5 of 20
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