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| 型号： | ADP1714AUJZ-3.0-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/16页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 3V .3A 5TSOT |
| 产品培训模块： | Power Line Monitoring |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 3V |
| 输入电压： | 最高 5.5V |
| 电压 - 压降（标准）： | 0.17V @ 300mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 300mA（最小值） |
| 电流 - 限制（最小）： | 380mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-5 细型，TSOT-23-5 |
| 供应商设备封装： | TSOT-23-5 |
| 包装： | 标准包装 |
| 产品目录页面： | 794 (CN2011-ZH PDF) |
| 其它名称： | ADP1714AUJZ-3.0-R7DKR |
ADP1712/ADP1713/ADP1714
THEORY OF OPERATION
The ADP1712/ADP1713/ADP1714 are low dropout linear regula-
tors that use an advanced, proprietary architecture to provide high
power supply rejection ratio (PSRR) and excellent line and load
transient response with just a small 2.2 μ F ceramic output capac-
itor. All devices operate from a 2.5 V to 5.5 V input rail and provide
up to 300 mA of output current. Incorporating a novel scaling
architecture, ground current is very low when driving light loads.
Ground current in the shutdown mode is typically less than 1 μA.
SOFT-START FUNCTION (ADP1712)
For applications that require a controlled startup, the ADP1712
provides a programmable soft-start function. Programmable soft
start is useful for reducing inrush current upon startup and for pro-
viding voltage sequencing. To implement soft start, connect a small
ceramic capacitor from SS to GND. Upon startup, a 1.2 μA current
source charges this capacitor. The ADP1712 start-up output voltage
is limited by the voltage at SS, providing a smooth ramp up to the
nominal output voltage. The soft-start time is calculated by
IN
OUT
T SS = V REF × ( C SS / I SS )
(1)
where:
T SS is the soft-start period.
CURRENT
LIMIT
THERMAL
PROTECT
V REF is the 0.8 V reference voltage.
C SS is the soft-start capacitance from SS to GND.
I SS is the current sourced from SS (1.2 μA).
EN
SHUTDOWN
AND UVLO
REFERENCE
SS/
ADJ/
BYP/
TRK
When the ADP1712 is disabled (using EN), the soft-start capacitor
is discharged to GND through an internal 100 Ω resistor.
GND
Figure 25. Internal Block Diagram
Internally, the ADP1712/ADP1713/ADP1714 each consist of a
reference, an error amplifier, a feedback voltage divider, and a
PMOS pass transistor. Output current is delivered via the PMOS
pass device, which is controlled by the error amplifier. The error
1
EN
amplifier compares the reference voltage with the feedback volt-
age from the output and amplifies the difference. If the feedback
voltage is lower than the reference voltage, the gate of the PMOS
2
OUT
V IN = 5V
V OUT = 3.3V
C OUT = 2.2 μ F
C SS = 22nF
I LOAD = 300mA
device is pulled lower, which allows more current to pass and
increases the output voltage. If the feedback voltage is higher than
the reference voltage, the gate of the PMOS device is pulled higher,
allowing less current to pass and decreasing the output voltage.
The ADP1712 is available in two versions, one with a fixed output
voltage and one with an adjustable output voltage. The fixed output
voltage is set internally to one of sixteen values between 0.75 V and
3.3 V, using an internal feedback network. The adjustable output
voltage can be set to between 0.8 V and 5.0 V by an external voltage
divider connected from OUT to ADJ. The ADP1713 and ADP1714
are available in fixed output voltage options only. The ADP1712
fixed version allows an external soft-start capacitor to be connected
between the SS pin and GND, which controls the output voltage
ramp during startup. The ADP1713 allows a reference bypass
capacitor to be connected between the BYP pin and GND, which
reduces output voltage noise and improves power supply rejection.
TIME (4ms/DIV)
Figure 26. OUT Ramp-Up with External Soft-Start Capacitor
The ADP1712 adjustable version, ADP1713, and ADP1714 have
no pins for soft start, so the function is switched to an internal
soft-start capacitor. This sets the soft-start ramp-up period to
approximately 24 μs.
EN
1
The ADP1714 features a track pin, which allows the output voltage
to follow the voltage at the TRK pin.
2
OUT
V IN = 5V
V OUT = 1.6V
C OUT = 2.2 μ F
I LOAD = 10mA
A logic on the EN pin determines if the output is active. When EN
is high, the output is on, and when EN is low, the output is off.
Rev. A | Page 10 of 16
TIME (20μs/DIV)
Figure 27. OUT Ramp-Up with Internal Soft-Start
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