参数资料
型号: ADP1879ACPZ-0.6-R7
厂商: Analog Devices Inc
文件页数: 6/40页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 14LFCSP
标准包装: 1,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 600kHz
占空比: 65%
电源电压: 2.95 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 14-WFDFN 裸露焊盘,CSP
包装: 带卷 (TR)

ADP1878/ADP1879
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADP1878/ADP1879
Data Sheet
VIN 1
COMP 2
EN 3
14
13
12
BST
SW
DRVH
FB
4
11 PGND
GND 5
RES 6
VREG 7
10
9
8
DRVL
PGOOD
SS
TOP VIEW
(Not to Scale)
NOTES
1. CONNECT THE EXPOSED PAD TO THE
ANALOG GROUND PIN (GND).
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
VIN
COMP
EN
FB
GND
RES
VREG
SS
PGOOD
DRVL
PGND
DRVH
SW
BST
EP
Description
High-Side Input Voltage. Connect VIN to the drain of the high-side MOSFET.
Output of the Error Amplifier. Connect compensation network between this pin and AGND to achieve stability (see
the Compensation Network section).
IC Enable. Connect EN to VREG to enable the IC. When pulled down to AGND externally, EN disables the IC.
Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.
Analog Ground Reference Pin of the IC. Connect all sensitive analog components to this ground plane (see the Layout
Considerations section).
Current Sense Gain Resistor (External). Connect a resistor between the RES pin and GND (Pin 5).
Internal Regulator Supply Bias Voltage for the ADP1878 / ADP1879 Controller (Includes the Output Gate Drivers).
Connecting a bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF capacitor across VREG and GND are
recommended.
Soft Start Input. Connect an external capacitor to GND to program the soft start period. There is a capacitance value
of 10 nF for every 1 ms of soft start delay.
Open-Drain Power-Good Output. PGOOD sinks current when FB is out of regulation or during thermal shutdown.
Connect a 3 kΩ resistor between PGOOD and VREG. Leave PGOOD unconnected if it is not used.
Drive Output for the External Low-Side, N-Channel MOSFET. This pin also serves as the current sense gain setting pin
Power Ground. Ground for the low-side gate driver and low-side N-channel MOSFET.
Drive Output for the External High-Side N-Channel MOSFET.
Switch Node Connection.
Bootstrap for the High-Side N-Channel MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected
between VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected
between VREG and BST for increased gate drive capability.
Exposed Pad. Connect the exposed pad to the analog ground pin (GND).
Rev. B | Page 6 of 40
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ADP1879ACPZ-1.0-R7 功能描述:IC REG CTRLR BUCK PWM CM 14LFCSP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR)
ADP1880ACPZ-R7 制造商:Analog Devices 功能描述:
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