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| 型号： | ADP2106ACPZ-1.8-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/36页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC 1.8V 16LFCSP |
| 产品培训模块： | Powering 90nm/65nm FPGAs and Processors |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 1.8V |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1.2MHz |
| 电流 - 输出： | 1.5A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VQFN 裸露焊盘，CSP |
| 包装： | 标准包装 |
| 供应商设备封装： | 16-LFCSP-VQ |
| 其它名称： | ADP2106ACPZ-1.8-R7DKR |
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ADP2105/ADP2106/ADP2107
THEORY OF OPERATION
The ADP2105/ADP2106/ADP2107 are step-down, dc-to-dc
converters that use a fixed frequency, peak current mode archi-
tecture with an integrated high-side switch and low-side synchron-
ous rectifier. The high 1.2 MHz switching frequency and tiny
16-lead, 4 mm × 4 mm LFCSP_VQ package allow for a small step-
down dc-to-dc converter solution. The integrated high-side switch
(P-channel MOSFET) and synchronous rectifier (N-channel
MOSFET) yield high efficiency at medium to heavy loads. Light
load efficiency is improved by smoothly transitioning to variable
frequency PFM mode.
The ADP2105/ADP2106/ADP2107 (ADJ) operate with an input
voltage from 2.7 V to 5.5 V and regulate an output voltage down
to 0.8 V. The ADP2105/ADP2106/ADP2107 are also available with
preset output voltage options of 3.3 V, 1.8 V, 1.5 V, and 1.2 V.
CONTROL SCHEME
The ADP2105/ADP2106/ADP2107 operate with a fixed frequency,
peak current mode PWM control architecture at medium to high
loads for high efficiency, but shift to a variable frequency PFM
control scheme at light loads for lower quiescent current. When
operating in fixed frequency PWM mode, the duty cycle of the
integrated switches is adjusted to regulate the output voltage, but
when operating in PFM mode at light loads, the switching
frequency is adjusted to regulate the output voltage.
The ADP2105/ADP2106/ADP2107 operate in the PWM mode
only when the load current is greater than the pulse-skipping
threshold current. At load currents below this value, the converter
smoothly transitions to the PFM mode of operation.
PWM MODE OPERATION
In PWM mode, the ADP2105/ADP2106/ADP2107 operate at a
fixed frequency of 1.2 MHz set by an internal oscillator. At the
start of each oscillator cycle, the P-channel MOSFET switch is
turned on, putting a positive voltage across the inductor. Current
in the inductor increases until the current sense signal crosses
the peak inductor current level that turns off the P-channel
MOSFET switch and turns on the N-channel MOSFET synchro-
nous rectifier. This puts a negative voltage across the inductor,
causing the inductor current to decrease. The synchronous
rectifier stays on for the remainder of the cycle, unless the
inductor current reaches zero, which causes the zero-crossing
comparator to turn off the N-channel MOSFET. The peak
inductor current is set by the voltage on the COMP pin. The
Data Sheet
PFM MODE OPERATION
The ADP2105/ADP2106/ADP2107 smoothly transition to the
variable frequency PFM mode of operation when the load current
decreases below the pulse skipping threshold current, switching
only as necessary to maintain the output voltage within regulation.
When the output voltage dips below regulation, the ADP2105/
ADP2106/ADP2107 enter PWM mode for a few oscillator cycles
to increase the output voltage back to regulation. During the wait
time between bursts, both power switches are off, and the output
capacitor supplies all the load current. Because the output voltage
dips and recovers occasionally, the output voltage ripple in this
mode is larger than the ripple in the PWM mode of operation.
PULSE-SKIPPING THRESHOLD
The output current at which the ADP2105/ADP2106/ADP2107
transition from variable frequency PFM control to fixed frequency
PWM control is called the pulse-skipping threshold. The pulse-
skipping threshold is optimized for excellent efficiency over all
load currents. The variation of pulse-skipping threshold with
100% DUTY CYCLE OPERATION (LDO MODE)
As the input voltage drops, approaching the output voltage, the
ADP2105/ADP2106/ADP2107 smoothly transition to 100%
duty cycle, maintaining the P-channel MOSFET switch-on conti-
nuously. This allows the ADP2105/ADP2106/ADP2107 to regulate
the output voltage until the drop in input voltage forces the P-
channel MOSFET switch to enter dropout, as shown in the
following equation:
V IN(MIN) = I OUT × ( R DS(ON) ? P + DCR IND ) + V OUT(NOM)
The ADP2105/ADP2106/ADP2107 achieve 100% duty cycle
operation by stretching the P-channel MOSFET switch-on time
if the inductor current does not reach the peak inductor current
level by the end of the clock cycle. When this happens, the oscil-
lator remains off until the inductor current reaches the peak
inductor current level, at which time the switch is turned off and
the synchronous rectifier is turned on for a fixed off time. At
the end of the fixed off time, another cycle is initiated. As the
ADP2105/ADP2106/ADP2107 approach dropout, the switching
frequency decreases gradually to smoothly transition to 100%
duty cycle operation.
COMP pin is the output of a transconductance error amplifier that
compares the feedback voltage with an internal 0.8 V reference.
Rev. D | Page 14 of 36
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