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参数资料
| 型号： | ADP2127ACNZ-1.20R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC 1.2V 0.5A 6EWLP |
| 产品变化通告： | 8mm Carrier Tape Changes 28/Feb/2012 |
| 标准包装： | 3,000 |
| 类型： | 降压（降压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 1.2V |
| 输入电压： | 2.1 V ~ 5.5 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 6MHz |
| 电流 - 输出： | 500mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-SMD，无引线 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 6-WLP Embedded（1.3x0.90） |
Data Sheet
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects both the output voltage
ripple and the loop dynamics of the converter. For a given loop
crossover frequency (the frequency at which the loop gain drops
to 0 dB), the maximum voltage transient excursion (overshoot)
ADP2126/ADP2127
The power dissipation (P D ) of the ADP2126 / ADP2127 is only a
portion of the power loss of the overall application. For a given
application with known operating conditions, the application
power loss is calculated by combining the following equations
for power loss (P LOSS ) and efficiency (η):
is inversely proportional to the value of the output capacitor.
P LOSS = P IN ? P OUT
(8)
η =
× 100
P OUT
When choosing output capacitors, it is important to account for
the loss of capacitance due to output voltage dc bias. This may
result in using a capacitor with a higher rated voltage to achieve
the desired capacitance value. Additionally, if ceramic output
capacitors are used, the capacitor’s rms ripple current rating
(9)
P IN
The resulting equation uses the output power and the efficiency
to determine the P LOSS .
L × f SW × V IN ( MAX )
? 1 ? ?
P LOSS = P OUT ? ?
η
should always meet or exceed the application requirements.
The rms ripple current is calculated from
1 V OUT × ( V IN ( MAX ) ? V OUT )
I RMS ( COUT ) = ×
2 3
(5)
? 100 ?
(10)
? ?
The power loss calculated using this approach is the combined
loss of the ADP2126/ADP2127 device (P D ), the inductor (P L ),
At nominal load currents, the converter operates in forced PWM
mode, and the overall output voltage ripple is the sum of the voltage
input capacitor (P CIN ), and the output capacitor (P COUT ), as
shown in the following equation:
spike caused by the output capacitor ESR plus the voltage ripple
P LOSS = P D + P L + P CIN + P COUT
(11)
caused by charging and discharging the output capacitor.
The power loss for the inductor, input capacitor, and output
Δ V OUT = Δ I L × ( ESR + 1/(8 × C OUT × f SW ))
(6)
capacitor is calculated using
? I
?
P CIN = ? RMS ? × ESR CIN
The largest voltage ripple occurs at the highest input voltage.
The ADP2126 / ADP2127 are designed to operate with one
small 2.2 μF capacitor. For a 0.22 mm height solution using the
ADP2127, at least 2 × 1.0 μF capacitors will be necessary on the
output. X5R or X7R dielectrics that have low ESR, low ESL, and
P L = I RMS 2 × DCR
2
? 2 ?
P COUT = (Δ IOUT ) 2 × ESR COUT
(12)
(13)
(14)
a voltage rating of 4 V or higher are recommended. These low
ESR components help the ADP2126/ADP2127 meet tight
If multilayer chip capacitors with low ESR are used, the power
loss in the input and output capacitors is negligible and
output voltage ripple specifications.
THERMAL CONSIDERATIONS
P D + P L >> P CIN + P COUT
P LOSS ≈ P D + P L
(15)
(16)
The operating junction temperature (T J ) of the device is
dependent on the ambient operating temperature (T A ) of the
application, the power dissipation of the ADP2126/ADP2127
The final equation for calculating P D can be used in Equation 7 to
ensure that the operating junction temperature is not exceeded.
P D ≈ P LOSS ? P L ≈ P OUT ? ?
? 1 ? ? ? P L
(P D ), and the junction-to-ambient thermal resistance of the
package (θ JA ). The operating junction temperature (T J ) is
calculated from
T J = T A + ( P D × θ JA )
(7)
? 100
? η
?
?
(17)
The ADP2126/ADP2127 may be damaged when the operating
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that the junction temperature
(T J ) is within the specified temperature limits.
?
?
In applications with high P D and poor PCB thermal
resistance, the maximum ambient temperature may
need to be derated.
In applications with moderate P D and good PCB thermal
resistance, the maximum ambient temperature can exceed
the maximum limit as long as the junction temperature is
within specification limits.
Rev. B | Page 15 of 20
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