参数资料
型号: ADP2302-EVALZ
厂商: Analog Devices Inc
文件页数: 20/28页
文件大小: 0K
描述: EVAL BOARD FOR ADP2302
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
电流 - 输出: 2A
输入电压: 3 ~ 20 V
稳压器拓扑结构: 降压
频率 - 开关: 700kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ADP2302

ADP2302/ADP2303
DESIGN EXAMPLE
This section provides the procedures to select the external compo-
nents, based on the example specifications listed in Table 10.
Data Sheet
The inductor peak current is calculated using the following
equation:
The schematic for this design example is shown in Figure 51.
Because the output current is 3 A, the ADP2303 is chosen for
this application.
Table 10. Step-Down DC-to-DC Regulator Requirements
I PEAK ? I LOAD (max) ?
where:
I LOAD(max) = 3 A.
? I RIPPLE
2
Parameter
Input Voltage, V IN
Output Voltage, V OUT
Programmable
UVLO Voltage
PGOOD
Specification
12.0 V ± 10%
3.3 V, 3 A, 1% V OUT ripple
at full load condition
V IN start-up voltage
approximately 7.8 V
Not used
Additional
Requirements
None
None
None
None
Δ I RIPPLE = 0.7 A.
The calculated peak current for the inductor is 3.4 A. Therefore,
in this application, select VLF10040T-4R7N5R4 as the inductor.
OUTPUT CAPACITOR SELECTION
Select the output capacitor based on the minimum output
voltage ripple requirement, according to the following equation:
? V RIPPLE ? ? I RIPPLE ? ? ?
?
?
CATCH DIODE SELECTION
Select the catch diode. A Schottky diode is recommended for best
efficiency because it has a low forward voltage drop and faster
switching speed. The average current of the catch diode in
normal operation, with a typical Schottky diode forward
voltage, can be calculated using the following equation:
? 1
? 8 ? f sw ? C OUT
where:
ΔI RIPPLE = 0.7 A.
f SW = 700 kHz.
Δ V RIPPLE = 33 mV (1% of output voltage).
? ESR C OUT
?
?
I DIODE ( AVG ) ? ? ? 1 ? OUT
V IN ? V D
? ? I LOAD (max)
?
where:
V OUT = 3.3 V.
V IN = 12 V.
I LOAD(max) = 3 A.
? V ? V D
?
?
?
If ESR of the ceramic capacitor is 3 mΩ, then C OUT = 4 μF.
Because the output capacitor is one of two external components
that control the loop stability and according to the recommended
external components in Table 11, choose two 47 μF capacitor
with a 6.3 V voltage rating in this application.
RESISTIVE VOLTAGE DIVIDER SELECTION
V OUT ? 0 . 800 V ? ? ? 1 ? TOP
?
?
V D = 0.4 V.
Therefore, I DIODE(AVG) = 2.1 A.
In this case, selecting a SSB43L, 4.0 A, 30 V surface-mount
Schottky diode results in more reliable operation.
INDUCTOR SELECTION
Select the inductor by using the following equation:
The output feedback resistive voltage divider is
? R ?
? R BOT ?
For the 3.3 V output voltage, choose R TOP = 31.6 kΩ and
R BOT = 10.2 kΩ as the feedback resistive voltage divider
according to the recommended values in Table 11.
? V IN ? V OUT ?
? ? ? OUT
V IN ? V D
?
?
? 1 . 2 μA ? ? ? R EN1 ? 1 . 2 V
V STARTUP ? ??
L ?
0 . 3 ? I LOAD (max) ? f sw
where:
V OUT = 3.3 V.
V IN = 12 V.
I LOAD(max) = 3 A.
V D = 0.4 V.
? V ? V D
?
?
?
The resistive voltage divider for the programmable V IN start-up
voltage is
? 1 . 2 V ?
? R EN2 ?
If V STARTUP = 7.8 V, choose R EN2 = 10.2 kΩ, and then calculate
R EN1 , which, in this case, is 56 kΩ.
f SW = 700 kHz.
This results in L = 4.12 μH. The closest standard value is 4.7 μH;
therefore, ΔI RIPPLE = 0.7 A.
Rev. A | Page 20 of 28
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