参数资料
型号: ADP2370ACPZ-R7
厂商: Analog Devices Inc
文件页数: 20/32页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 0.8A 8LFCSP
标准包装: 1,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 12 V
输入电压: 3.2 V ~ 15 V
PWM 型: 电流模式
频率 - 开关: 600kHz ~ 1.2MHz
电流 - 输出: 800mA
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-WDFN 裸露焊盘,CSP
包装: 带卷 (TR)
供应商设备封装: 8-LFCSP(3x3)

ADP2370/ADP2371
THEORY OF OPERATION
Data Sheet
EN
1.2V
1.0V
EN_PREC
STANDBY
1.2A
P_I LIMIT
V SW
VIN
5V
REG
VIN
VIN
UVLO
VIN
2.95V
RDS ON × Kr
I MIN
200mA
Kr
VIN
N_I LIMIT
–0.5A – (PWM)
SW
0A – (PSM)
RDS ON × Kr
PWM
CONTROL
VIN
ADP2371
ONLY
LOGIC
SLOPE COMP I SLOPE
0.808V
0.8V
PSM
PGND
SYNC
FSEL
H = FPWM
L = PWM/PSM
H = 1.2MHz
L = 600kHz
150°C
THSD
135°C
OSCILLATOR
DEFAULT = 1.2MHz
VOUT ÷ 2 FREQUENCY
FOLDBACK
FB
PG
0.736V
I COMP
V TOL
V COMP
g M
0.8V
0.696V
FB
SOFT
START
Figure 71. Functional Block Diagram
1 . 2 × V OUT
0 . 478 × f SW
The ADP2370 / ADP2371 use a high speed, current mode, constant
frequency PWM control scheme for excellent stability and tran-
sient response. To ensure the longest battery life in portable
applications, the ADP2370 / ADP2371 has a power saving mode.
Under light load conditions, the output capacitor is charged as
needed to maintain regulation; otherwise, the ADP2370 / ADP2371
enter sleep mode, a low 14 μA quiescent state. The architecture
ensures smooth transitions from PWM mode to and from PSM,
and maintains high efficiencies at light loads. The following sec-
tions describe the two modes of operation and provide detailed
descriptions of the ADP2370 / ADP2371 features.
PWM OPERATION
The ADP2370 / ADP2371 PWM mode is a fixed frequency,
1.2 MHz typical, current mode architecture. Use the SYNC pin
to synchronize the regulator to an external clock frequency or
use the FSEL pin to select an internal clock frequency of
600 kHz or 1.2 MHz.
The ADP2370 / ADP2371 use a constant slope compensation
scheme where the inductor scales with the output voltage. The
equation for choosing the inductor for a particular output
voltage is
L =
See the Applications Information section for details regarding
choosing an appropriate inductor value.
Cycle to cycle operation of the PWM mode begins with the
falling edge of the internal clock. Note that when using an
external clock, the rising edge synchronizes the regulator and
the falling edge is determined by the internal clock, typically a
25 ns pulse width. The falling edge of the clock starts the cycle
by turning on the high-side switch, which produces a positive
di/dt current in the inductor. The PWM comparator controls
when the high-side switch turns off. The positive input of the
comparator monitors the peak inductor current via the SW node.
Rev. D | Page 20 of 32
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ADP2370ACPZ-5.0-R7 IC REG BUCK SYNC 5V 0.8A 8LFCSP
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