参数资料
型号: ADP2370ACPZ-R7
厂商: Analog Devices Inc
文件页数: 26/32页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 0.8A 8LFCSP
标准包装: 1,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 12 V
输入电压: 3.2 V ~ 15 V
PWM 型: 电流模式
频率 - 开关: 600kHz ~ 1.2MHz
电流 - 输出: 800mA
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-WDFN 裸露焊盘,CSP
包装: 带卷 (TR)
供应商设备封装: 8-LFCSP(3x3)
V OUT
ADP2370/ADP2371
To minimize errors in the output voltage caused by the bias
current of the FB pin, maintain a value of R2 that is less than
250 kΩ. For example, when R2 and R3 each equal 250 kΩ, the
output voltage is 1.6 V. The output voltage error introduced by
the FB pin bias current is 2.5 mV, or 0.156%, assuming a typical
FB pin bias current of 10 nA at 25°C.
Note that in shutdown mode, the output is turned off and the
divider current is zero.
Select the output inductor and capacitor as described in the
Selecting the Inductor, Output Capacitor, and Input Capacitor
sections, as well as Table 6 for more information.
EFFICIENCY
Efficiency is defined as the ratio of output power to input power.
The high efficiency of the ADP2370/ADP2371 has two distinct
advantages. First, only a small amount of power is lost in the
dc-to-dc converter package, which in turn, reduces thermal
constraints. Second, high efficiency delivers the maximum
output power for the given input power, thereby extending
battery life in portable applications.
Power Switch Conduction Losses
Power switch dc conduction losses are caused by the flow of
output current through the P-channel power switch and the
N-channel synchronous rectifier, which have internal resis-
tances (R DS(ON) ) associated with them. The amount of power
loss is approximated by
P SW _ COND = ( R DS ( ON ) _ P × D + R DS ( ON ) _ N × ( 1 ? D )) × I OUT 2
where:
D =
V IN
The internal resistance of the power switches increases with tem-
perature and increases when the input voltage is less than 5.5 V.
Inductor Losses
Inductor conduction losses are caused by the flow of current
Data Sheet
Switching Losses
Switching losses are associated with the current drawn by the
driver to turn-on and turn-off the power devices at the switching
frequency. Each time a power device gate is turned on and turned
off, the driver transfers a charge from the input supply to the
gate, and then from the gate to ground.
Estimate switching losses using the following equation:
P SW = ( C GATE_P + C GATE_N ) × V IN 2 × f SW
where:
C GATE_P is the gate capacitance of the internal high-side switch.
C GATE_N is the gate capacitance of the internal low-side switch.
f SW is the switching frequency.
The typical value for gate capacitances, C GATE_P and C GATE_N ,
is 150 pF.
Transition Losses
Transition losses occur because the P-channel switch cannot
turn on or turn off instantaneously. In the middle of an SW
node transition, the power switch provides all of the inductor
current. The source-to-drain voltage of the power switch is half
the input voltage, resulting in power loss. Transition losses
increase with both load current and input voltage and occur
twice for each switching cycle.
Use the following equation to estimate transition losses:
P TRAN = V IN /2 × I OUT × ( t R + t F ) × f SW
where:
t R is the rise time of the SW node.
t F is the fall time of the SW node.
The typical value for the rise and fall times, t R and t F , is 2 ns.
RECOMMENDED BUCK EXTERNAL COMPONENTS
The recommended external components for use with the
ADP2370 / ADP2371 are listed in Table 6 (inductors) and Table 7
(capacitors).
V IN = 6V
through the inductor, which has an internal resistance (DCR)
associated with it. Larger size inductors have smaller DCR,
which can decrease inductor conduction losses. Inductor core
losses relate to the magnetic permeability of the core material.
Because the ADP2370 / ADP2371 are high switching frequency
C IN
10μF
VIN
1
ADP2370/
ADP2371
8
PGND
POWER GOOD
dc-to-dc regulators, shielded ferrite core material is recommended
because of its low core losses and low EMI.
To estimate the total amount of power lost in the inductor, use
the following equation:
OFF
ON
FSEL
EN
2
3
AGND
(EXPOSED PAD)
7
6
SW
PG
6.8μH
V OUT = 3.3V
C OUT
10μF
P L = DCR × I OUT + Core Losses
2
SYNC
4
5
FB
Figure 82. Typical Application, 1.2 MHz, Fixed Output
Rev. D | Page 26 of 32
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ADP2370ACPZ-5.0-R7 IC REG BUCK SYNC 5V 0.8A 8LFCSP
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