参数资料
型号: ADP2370ACPZ-R7
厂商: Analog Devices Inc
文件页数: 23/32页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 0.8A 8LFCSP
标准包装: 1,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 12 V
输入电压: 3.2 V ~ 15 V
PWM 型: 电流模式
频率 - 开关: 600kHz ~ 1.2MHz
电流 - 输出: 800mA
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-WDFN 裸露焊盘,CSP
包装: 带卷 (TR)
供应商设备封装: 8-LFCSP(3x3)
Data Sheet
100% DUTY CYCLE
The ADP2370 / ADP2371 enter and exit 100% duty cycle smoothly.
The control loop seeks the next clock cycle while the high-side
switch is engaged. When this occurs, the clock signal is masked
and the PMOS remains on. When the input voltage increases, the
internal V COMP node decreases its signal to the control loop; thus,
the device stops skipping clock cycles and exits 100% duty cycle.
ADP2370/ADP2371
If the device is synchronized to an external clock, the PSM
mode is disabled and the device stays in forced PWM mode.
Connect FSEL to ground when synchronizing to a frequency
range from 400 kHz to 800 kHz, and connect FSEL to the input
voltage when the external frequency is in the range of 800 kHz
to 1600 kHz. FSEL has an internal pull-down resistor and
defaults to the 600 kHz mode when FSEL is unconnected.
V IN
INTERNAL 1.2MHZ
1
2
3
4
1
INTERNAL 600kHZ
V OUT
SYNC
2
PWM CLOCK (IF FSEL = 1)
PWM CLOCK (IF FSEL = 0)
3
INDUCTOR CURRENT
PWM CLOCK FOLLOWS SYNC UNTIL IT MISSES
CH1 1.00V
W
B
CH3 50.0mA ? BW
CH2 1.00V BW
M2.00ms
T 32.20%
A CH1
4.90V
4 × 1.2MHZ INTERNAL CLOCK CYCLES
Figure 76. Typical SYNC Timing
Figure 74. Transition into and out of Dropout in PSM Mode,
V IN
V OUT = 5 V, 100 mA Load
1
SW
V OUT
V OUT
2
INDUCTOR CURRENT
3
SYNC
INDUCTOR CURRENT
4
W
W
1
3 2
CH1 5.00V BW CH2 100mV
CH3 200mA ? BW CH4 5.00V
B
B
M20.0μs
T 20.0%
A CH4
2.00V
CH1 1.00V BW
CH3 50.0mA ? BW
CH2 1.00V BW
M2.00ms
T 32.20%
A CH1
4.90V
Figure 77. Typical SYNC Transient, 1.2 MHz to 800 kHz to 1.2 MHz
Figure 75. Transition into and out of Dropout in PWM Mode,
V OUT = 5 V, 100 mA Load
SYNCHRONIZING
1
SW
It is possible to synchronize the ADP2370/ADP2371 to an external
clock within a frequency range from 400 kHz to 1.6 MHz. The
device automatically detects the rising edge of the first clock
and synchronizes to the external clock. When the clock signal
2
V OUT
INDUCTOR CURRENT
stops, the device automatically switches back to the internal
clock and continues operating.
The switchover is initiated when no rising edge on the SYNC
3
SYNC
W M20.0μs A CH4
W
pin can be detected on the internal clock for a duration of four
clock cycles. Therefore, the maximum delay time can be 6.7 μs if
the internal clock is running at its minimum frequency of 600 kHz.
4
CH1 5.00V BW CH2 50.0mV
CH3 200mA ? BW CH4 5.00V
B
B
T 20.0%
2.00V
During this time, there is no clock signal available. The output
stops switching until the ADP2370 circuitry switches to the
internal clock signal.
Rev. D | Page 23 of 32
Figure 78. SYNC Transient 1.2 MHz to 800 kHz
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ADP2370ACPZ-5.0-R7 IC REG BUCK SYNC 5V 0.8A 8LFCSP
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