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| 型号： | ADP3334ARMZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ .5A 8MSOP |
| 设计资源： | Broadband Low EVM Direct Conversion Transmitter (CN0134) Broadband Low EVM Direct Conversion Transmitter Using LO Divide-by-2 Modulator (CN0144) |
| 标准包装： | 1 |
| 系列： | anyCAP® |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 1.5 V ~ 10 V |
| 输入电压： | 2.6 V ~ 11 V |
| 电压 - 压降（标准）： | 0.2V @ 500mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 500mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 标准包装 |
| 其它名称： | ADP3334ARMZ-REEL7DKR |
ADP3334
To have the lowest possible sensitivity of the output voltage to
temperature variations, it is important that the value of the parallel
resistance of R 1 and R 2 be kept as close as possible to 50 k W .
3.0
2.5
R 1 ￥ R 2
R 1 + R 2
= 50 k W
(1)
2.0
Also, for the best accuracy over temperature, the feedback volt-
age should be set for 1.178 V:
1.5
￥ á
?
V FB = V OUT
ê R 2 ?
? R 1 + R 2 ˉ
(2)
1.0
0.5
where V OUT is the desired output voltage and V FB is the virtual
0
band gap voltage. Note that V FB does not actually appear at the
FB pin due to loading by the internal PTAT current.
0
2
3 4
Rp ERROR – %
5
6
Combining the above equations and solving for R 1 and R 2 gives
the following formulas:
Figure 4. Output Voltage Error vs.
Parallel Resistance Error
R 1 = 50 k W ￥ á OUT ?
R 2 =
á 1 - V
?
OUT ˉ
V OUT = 1 . 178 V ￥ á
+ 1 ?
? ˉ
ê V FB ?
ê V ?
? V FB ˉ
50 k W
?
Table I. Feedback Resistor Selection
(3)
(4)
The actual output voltage can be calculated using the following
equation.
ê R 1 ?
R 2
(5)
V OUT = 3 . 274 V
So worst-case error will occur when R1 has a –1% tolerance and
R2 has a +1% tolerance. Recalculating the output voltage, the
parallel resistance and error are:
V OUT = 1 . 178 V ￥ á
+ 1 ?
V OUT (V )
1.5
R1 (1% Resistor) (k )
63.4
R2 (1% Resistor) (k )
232.0
ê 138 . 6
? 79 . 5
?
ˉ
Resistor Divider Error = á
- 1 ? ￥ 100 % = - 2 . 1 %
R PARALLEL =
=
= 50 . 51 k W
Error = á
- 1 ? ￥ 100 % = 1 . 02 %
ê 50 . 51 ?
? 50
ˉ
1.8 76.8 147.0
2.2 93.1 107.0
2.7 115.0 88.7
3.3 140.0 78.7
5.0 210.0 64.9
10.0 422.0 56.2
Using standard 1% values, as shown in Table I, will sacrifice
some output voltage accuracy. To estimate the overall output
voltage accuracy, it is necessary to take into account all sources
V OUT = 3 . 232 V
R 1 ￥ R 2 138 . 6 ￥ 79 . 5
R 1 + R 2 138 . 6 + 79 . 5
R PARALLEL
ê 3 . 232 ?
? 3 . 3 ˉ
(6)
(7)
of error. The accuracy given in the specifications table does not
take into account the error introduced by the feedback resistor
divider ratio or the error introduced by the parallel combination
of the feedback resistors.
The error in the parallel combination of the feedback resistors
causes the reference to have a wider variation over temperature.
To estimate the variation, calculate the worst-case error from
50 k W , and then use the graph in Figure 4 to estimate the
additional change in the output voltage over the operating
temperature range.
For example:
V IN = 5 V
V OUT = 3.3 V
R1 = 140 k W , 1%
R2 = 78.7 k W , 1%
REV. C
–7 –
So, from the graph in Figure 4, the output voltage error is
estimated to be an additional 0.25%. The error budget is
1.8% (the initial output voltage accuracy over temperature),
plus 2.1% (resistor divider error), plus 0.25% (parallel resis-
tance error) for a worst-case total of 4.15%.
Thermal Overload Protection
The ADP3334 is protected against damage from excessive power
dissipation by its thermal overload protection circuit, which limits
the die temperature to a maximum of 165°C. Under extreme
conditions (i.e., high ambient temperature and power dissipation)
where die temperature starts to rise above 165°C, the output
current is reduced until the die temperature has dropped to a safe
level. The output current is restored when the die temperature
is reduced.
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