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| 型号： | ADP3419JRMZ-REEL |
| 厂商： | ON Semiconductor |
| 文件页数： | 7/10页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DVR DUAL BOOTST 10MSOP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi |
| 标准包装： | 1 |
| 配置： | 高端和低端，同步 |
| 输入类型： | PWM |
| 延迟时间： | 32ns |
| 电流 - 峰： | 1A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 30V |
| 电源电压： | 4.6 V ~ 6 V |
| 工作温度： | 0°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 1128 (CN2011-ZH PDF) |
| 其它名称： | ADP3419JRMZ-REELDKR |
ADP3419
Theory of Operation
The ADP3419 is a dual MOSFET driver optimized for
driving two N-channel MOSFETs in a synchronous buck
converter topology. A single PWM input signal is all that is
required to properly drive the high-side and the low-side
MOSFETs. Each driver is capable of driving a 3 nF load at
speeds up to 1 MHz. A more detailed description of the
ADP3419 and its features follows. Refer to the detailed
block diagram in Figure 16.
High-Side Driver
The high-side driver is designed to drive a floating low
R DS(ON) N-channel MOSFET. The bias voltage for the
high-side driver is developed by an external bootstrap supply
circuit, which is connected between the BST and SW pins.
The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, C BST . When the ADP3419 is starting up, the SW
pin is at ground, so the bootstrap capacitor charges up to
VCC through D1. Once the supply voltage ramps up and
CROWBAR 4
5V
VCC
5
UVLO
AND BIAS
D1
ADP3419
V DCIN
exceeds the UVLO threshold, the driver is enabled. When IN
goes high, the high-side driver begins to turn on the
high-side MOSFET (Q1) by transferring charge from C BST .
As Q1 turns on, the SW pin rises up to V DCIN , forcing the
BST pin to V DCIN + V C(BST) , which is enough
gate-to-source voltage to hold Q1 on. To complete the cycle,
Q1 is switched off by pulling the gate down to the voltage at
C BST
IN 1
SD 2
OVERLAP
PROTECTION
AND
TIME ? OUT
CIRCUIT
VCC
10
9
8
6
BST
R BST
DRVH
SW
DRVL
+
Q1
the SW pin. When the low-side MOSFET (Q2) turns on, the
SW pin is pulled to ground. This allows the bootstrap
capacitor to charge up to VCC again.
When the driver is enabled, the driver ’s output is in phase
with the IN pin. Table 2 shows the relationship between
DRVH and the different control inputs of the ADP3419.
Overlap Protection Circuit
The overlap protection circuit prevents both main power
DRVLSD 3
7
GND
Q2
switches, Q1 and Q2, from being on at the same time. This
is done to prevent shoot-through currents from flowing
through both power switches and the associated losses that
Figure 16. Detailed Block Diagram of the ADP3419
Undervoltage Lockout
The undervoltage lockout (UVLO) circuit holds both
MOSFET driver outputs low during VCC supply ramp-up.
The UVLO logic becomes active and in control of the driver
outputs at a supply voltage of no greater than 1.5 V. The
UVLO circuit waits until the VCC supply has reached a
voltage high enough to bias logic level MOSFETs fully on
before releasing control of the drivers to the control pins.
Driver Control Input
The driver control input (IN) is connected to the duty ratio
modulation signal of a switch-mode controller. IN can be
driven by 2.5 V to 5.0 V logic. The output MOSFETs are
driven so that the SW node follows the polarity of IN.
Low-Side Driver
The low-side driver is designed to drive a
ground-referenced low R DS(ON) N-channel synchronous
rectifier MOSFET. The bias to the low-side driver is
internally connected to the VCC supply and GND. Once the
supply voltage ramps up and exceeds the UVLO threshold,
the driver is enabled. When the driver is enabled, the driver’s
output is 180 ° out of phase with the IN pin. Table 2 shows
the relationship between DRVL and the different control
inputs of the ADP3419.
can occur during their on-off transitions. The overlap
protection circuit accomplishes this by adaptively
controlling the delay from Q1’s turn-off to Q2’s turn-on, and
the delay from Q2’s turn-off to Q1’s turn-on.
To prevent the overlap of the gate drives during Q1’s
turn-off and Q2’s turn-on, the overlap circuit monitors the
voltage at the SW pin and DRVH pin. When IN goes low, Q1
begins to turn off. The overlap protection circuit waits for
the voltage at the SW and DRVH pins to both fall below
1.6 V. Once both of these conditions are met, Q2 begins to
turn on. Using this method, the overlap protection circuit
ensures that Q1 is off before Q2 turns on, regardless of
variations in temperature, supply voltage, gate charge, and
drive current. There is, however, a timeout circuit that
overrides the waiting period for the SW and DRVH pins to
reach 1.6 V. After the timeout period has expired, DRVL is
asserted high regardless of the SW and DRVH voltages. In
the opposite case, when IN goes high, Q2 begins to turn off
after a propagation delay. The overlap protection circuit
waits for the voltage at DRVL to fall below 1.6 V, after which
DRVH is asserted high and Q1 turns on.
Low-Side Driver Shutdown
The low-side driver shutdown DRVLSD allows a control
signal to shut down the synchronous rectifier. Under light
load conditions, DRVLSD should be pulled low before the
polarity reversal of the inductor current to maximize light
load conversion efficiency. DRVLSD can also be pulled low
for reverse voltage protection purposes.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADP3419JRMZ-REEL1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Bootstrapped, High Voltage MOSFET Driver with Output Disable |
| ADP34200002RUR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADP3421 | 制造商:AD 制造商全称:Analog Devices 功能描述:Geyserville-Enabled DC-DC Converter Controller for Mobile CPUs |
| ADP3421JRU | 制造商:AD 制造商全称:Analog Devices 功能描述:Geyserville-Enabled DC-DC Converter Controller for Mobile CPUs |
| ADP3421JRU-REEL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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