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参数资料
型号： ADS1217IPFBR
英文描述： 8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER
中文描述： 8通道，24位模拟数字转换器
文件页数： 15/28页
文件大小： 458K
代理商： ADS1217IPFBR
ADS1217
SBAS260B
15
www.ti.com
When the DSYNC command is sent, the filter counter is reset
on the edge of the last SCLK on the DSYNC command. The
modulator is held in reset until the next edge of SCLK is
detected. Synchronization occurs on the next rising edge of
the system clock after the first SCLK after the DSYNC
command. After a DSYNC operation,
DRDY
is held HIGH
until valid data is ready.
RESET
There are three methods to reset the ADS1217: the
RESET
input, the RESET command, and a special SCLK input pat-
tern. When using the
RESET
input, take it LOW to force a
reset. Make sure to follow the minimum pulse width timing
specifications before taking the
RESET
input back high. Also,
avoid glitches on the
RESET
input as these may cause
accidental resets. The RESET command takes effect after all
8 bits have been shifted into DIN. Afterwards, the reset
releases automatically. The ADS1217 can also be reset with
a special pattern on SCLK, see the Timing Diagram. Reset
occurs on the falling edge of the last SCLK edge in the pattern
(for POL = 0). Afterwards, the reset releases automatically.
POWER-UP
—
SUPPLY VOLTAGE RAMP RATE
The power-on reset circuitry was designed to accommodate
digital supply ramp rates as slow as 1V/10ms. To ensure
proper operation, the power supply should ramp monotonically.
MEMORY
Two types of memory are used on the ADS1217: registers
and RAM. 16 registers directly control the various functions
(PGA, DAC value, Decimation Ratio, etc.) and can be directly
read or written. Collectively, the registers contain all the
information needed to configure the part, such as data
format, mux settings, calibration settings, decimation ratio,
etc. Additional registers, such as output data, are accessed
through dedicated instructions.
REGISTER BANK TOPOLOGY
The operation of the device is set up through individual
registers. The set of the 16 registers required to configure the
device is referred to as a Register Bank, as shown in Figure 5.
Reads and Writes to Registers and RAM occur on a byte
basis. However, copies between registers and RAM occurs
on a bank basis. The RAM is independent of the Registers;
that is, the RAM can be used as general-purpose RAM.
The ADS1217 supports any combination of eight analog
inputs. With this flexibility, the device could easily support
eight unique configurations
—
one per input channel. In order
to facilitate this type of usage, eight separate register banks
are available. Therefore, each configuration could be written
once and recalled as needed without having to serially
retransmit all the configuration data. Checksum commands
are also included, which can be used to verify the integrity of
RAM.
Configuration
Registers
16 bytes
SETUP
MUX
ACR
IDAC1
IDAC2
ODAC
DIO
DIR
DEC0
M/DEC1
OCR0
OCR1
OCR2
FSR0
FSR1
FSR2
RAM
128 Bytes
Bank 2
16 bytes
Bank 7
16 bytes
Bank 0
16 bytes
The RAM provides eight
“
banks
”
, with a bank consisting of
16 bytes. The total size of the RAM is 128 bytes. Copies
between the registers and RAM are performed on a bank
basis. Also, the RAM can be directly read or written through
the serial interface on power-up. The banks allow separate
storage of settings for each input.
The RAM address space is linear, therefore accessing RAM
is done using an auto-incrementing pointer. Access to RAM
in the entire memory map can be done consecutively with-
out having to address each bank individually. For example,
if you were currently accessing bank 0 at offset 0F
H
(the last
location of bank 0), the next access would be bank 1 and
offset 00
H
. Any access after bank 7 and offset 0F
H
will wrap
around to bank 0 and Offset 00
H
.
Although the Register Bank memory is linear, the concept of
addressing the device can also be thought of in terms of
bank and offset addressing. Looking at linear and bank
addressing syntax, we have the following comparison: in the
linear memory map, the address 14
H
is equivalent to bank
1 and offset 04
H
. Simply stated, the most significant four bits
represent the bank, and the least significant four bits repre-
sent the offset. The offset is equivalent to the register
address for that bank of memory.
FIGURE 5. Memory Organization.
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相关代理商/技术参数
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