参数资料
型号: ADS1217IPFBR
英文描述: 8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER
中文描述: 8通道,24位模拟数字转换器
文件页数: 19/28页
文件大小: 458K
代理商: ADS1217IPFBR
ADS1217
SBAS260B
19
www.ti.com
RDATA
Read Data
Description:
Read a single 24-bit ADC conversion result. On
completion of read back,
DRDY
goes HIGH.
Operands:
Bytes:
Encoding:
Data Transfer Sequence:
None
1
0000 0001
COMMANDS
DESCRIPTION
COMMAND BYTE
2ND COMMAND BYTE
RDATA
RDATAC
STOPC
RREG
RRAM
CREG
CREGA
WREG
WRAM
CRAM
CSRAMX
CSARAMX
CSREG
CSRAM
CSARAM
SELFCAL
SELFOCAL
SELFGCAL
SYSOCAL
SYSGCAL
WAKEUP
DSYNC
SLEEP
RESET
Read Data
0000 0001 (01
H
)
0000 0011 (03
H
)
0000 1111 (0F
H
)
0001 r r r r (1x
H
)
0010 0aaa (2x
H
)
0100 0aaa (4x
H
)
0100 1000 (48
H
)
0101 r r r r (5x
H
)
0110 0aaa (6x
H
)
1100 0aaa (Cx
H
)
1101 0aaa (Dx
H
)
1101 1000 (D8
H
)
1101 1111 (DF
H
)
1110 0aaa (Ex
H
)
1110 1000 (E8
H
)
1111 0000 (F0
H
)
1111 0001 (F1
H
)
1111 0010 (F2
H
)
1111 0011 (F3
H
)
1111 0100 (F4
H
)
1111 1011 (FB
H
)
1111 1100 (FC
H
)
1111 1101 (FD
H
)
1111 1110 (FE
H
)
Read Data Continuously
Stop Read Data Continuously
Read from REG Bank rrrr
Read from RAM Bank aaa
Copy REGs to RAM Bank aaa
Copy REGS to all RAM Banks
Write to REG rrrr
Write to RAM Bank aaa
Copy RAM Bank aaa to REG
Calc RAM Bank aaa Checksum
Calc all RAM Bank Checksum
Calc REG Checksum
Calc RAM Bank aaa Checksum
Calc all RAM Banks Checksum
Self Cal Offset and Gain
Self Cal Offset
Self Cal Gain
Sys Cal Offset
Sys Cal Gain
Wake Up From Sleep Mode
Sync DRDY
Put in Sleep Mode
Reset to Power-Up Values
xxxx_nnnn (# of reg-1)
xnnn_nnnn (# of bytes-1)
xxxx_nnnn (# of reg-1)
xnnn_nnnn (# of bytes-1)
NOTE: (1) The data received by the A/D converter is always MSB First, the data out format is set by the BIT ORDER bit in ACR reg.
TABLE III. Command Summary.
RDATAC
Read Data Continuous
Description:
Read Data Continuous mode enables the con-
tinuous output of new data on each
DRDY
. This command
eliminates the need to send the Read Data Command on each
DRDY
. This mode may be terminated by either the STOP
Read Continuous command or the RESET command.
Operands:
Bytes:
Encoding:
Data Transfer Sequence:
Command terminated when uuuu uuuu equals STOPC
or RESET.
None
1
0000 0011
NOTE: (1) For wait time, refer to timing specification.
D
IN
0000 0011
(1)
uuuu uuuu
uuuu uuuu
uuuu uuuu
D
OUT
D
IN
uuuu uuuu
uuuu uuuu
D
OUT
MSB
Mid-Byte
uuuu uuuu
LSB
DRDY
MSB
Mid-Byte
LSB
COMMAND DEFINITIONS
The commands listed below control the operation of the
ADS1217. Some of the commands are stand-alone com-
mands (e.g., RESET) while others require additional bytes
(e.g., WREG requires command, count, and the data bytes).
Commands that output data require a minimum of four f
OSC
cycles before the data is ready (e.g., RDATA).
Operands:
n = count (0 to 127)
r = register (0 to 15)
x = don
t care
a = RAM bank address (0 to 7)
D
IN
0000 0001
(1)
xxxx xxxx
xxxx xxxx
xxxx xxxx
D
OUT
MSB
Mid-Byte
LSB
DRDY
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