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参数资料
| 型号： | ADS1244IDGSR |
| 厂商： | Texas Instruments |
| 文件页数： | 2/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC LP CONVERT 24BIT 10-MSOP |
| 产品培训模块： | Data Converter Basics |
| 视频文件： | Nuts and Bolts of the Delta-Sigma Converter |
| 标准包装： | 2,500 |
| 位数： | 24 |
| 采样率（每秒）： | 15 |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 270µW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，单极；1 个差分，双极 |
| 配用： | 296-18359-ND - EVALUATION MODULE FOR ADS1244 |
ADS1244
10
SBAS273
www.ti.com
POWER-UP
Self-calibration is performed at power-up to minimize offset and
gain errors. In order for the self-calibration at power-up to work
properly, make sure that both AVDD and DVDD increase
monotonically and are settled by t1, as shown in Figure 11.
SCLK must be held LOW during this time. Once calibration is
complete, DRDY/DOUT will go LOW indicating data is ready
for retrieval. The time required before the first data is ready (t6)
depends on how fast AVDD and DVDD ramp to their final value
(t1). For most ramp rates, t1 + t2 ≈ 350ms (fCLK = 2.4576MHz).
If the system environment is not stable during power-up (the
temperature is varying or the supply voltages are moving
around), it is recommended that a self-calibration be issued
after everything is stable.
DATA FORMAT
The ADS1244 outputs 24 bits of data in Binary Two’s
Complement format. The Least Significant Bit (LSB) has a
weight of (2VREF)/(223 – 1). A positive full-scale input pro-
FIGURE 11. Power-Up Timing.
AVDD and DVDD
DRDY/DOUT
SCLK
t
1
t
2
Data ready after power-up calibration.
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
t1(1)
AVDD and DVDD settling time.
100
ms
t2(1)
Wait time for calibration and first data conversion.
316
ms
NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional
to CLK period.
duces an output code of 7FFFFFH and the negative full-scale
input produces an output code of 800000H. The output clips
at these codes for signals exceeding full-scale. Table I
summarizes the ideal output codes for different input signals.
INPUT SIGNAL VIN (AINP – AINN)
IDEAL OUTPUT CODE(1)
≥ +2V
REF
7FFFFFH
+
2
21
23
VREF
000001H
0
000000H
2
21
23
VREF
FFFFFFH
≤
2
21
23
VREF
800000H
NOTE: (1) Excludes effects of noise, INL, offset, and gain errors.
TABLE I. Ideal Output Code versus Input Signal.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADS1244IDGSRG4 | 功能描述:模数转换器 - ADC 24-Bit Delta-Sigma 15SPS w/50-60Hz rej RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ADS1244IDGST | 功能描述:模数转换器 - ADC 24-Bit Delta-Sigma 15SPS w/50-60Hz rej RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ADS1244IDGSTG4 | 功能描述:模数转换器 - ADC 24-Bit Delta-Sigma 15SPS w/50-60Hz rej RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ADS1245 | 制造商:BB 制造商全称:BB 功能描述:Low-Power, 24-Bit Analog-to-Digital Converter |
| ADS1245IDGSR | 功能描述:模数转换器 - ADC 24-bit Low-Power w/Hi-Z Input Buffer RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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