参数资料
型号: ADS1244IDGSR
厂商: Texas Instruments
文件页数: 24/24页
文件大小: 0K
描述: IC ADC LP CONVERT 24BIT 10-MSOP
产品培训模块: Data Converter Basics
视频文件: Nuts and Bolts of the Delta-Sigma Converter
标准包装: 2,500
位数: 24
采样率(每秒): 15
数据接口: 串行
转换器数目: 1
功率耗散(最大): 270µW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 带卷 (TR)
输入数目和类型: 2 个单端,单极;1 个差分,双极
配用: 296-18359-ND - EVALUATION MODULE FOR ADS1244
ADS1244
9
SBAS273
www.ti.com
To help see the response at lower frequencies, Figure 7
illustrates the response out to 180Hz. Notice that both 50Hz
and 60Hz signals are rejected. This feature is very useful for
eliminating power line cycle interference during measure-
ments. Figure 8 shows the ADS1244’s response around
these frequencies.
The ADS1244’s data rate and frequency response scale
directly with CLK frequency. For example, if fCLK increases
from 2.4576MHz to 4.9152MHz, the data rate increases from
15sps to 30sps while the notches in the response at 50Hz
and 60Hz move out to 100Hz and 120Hz.
SETTLING TIME
The ADS1244 has single-cycle settling. That is, the output
data is fully settled after a single conversion—there is no
need to wait for additional conversions before retrieving the
data when there is a change on the analog inputs.
In order to realize single-cycle settling, synchronize changes
on the analog inputs to the conversion beginning, which is
indicated by the falling edge of DRDY/DOUT. For example,
when using a multiplexer in front of the ADS1244, change the
multiplexer’s inputs when DRDY/DOUT goes LOW. Increas-
ing the time between the conversion beginning and the
change on the analog inputs (tDELAY) will result in a settling
error in the conversion data, as shown in Figure 9. The
settling error versus delay time is shown in Figure 10. If the
input change is delayed to the point where the settling error
is too high, simply ignore the first data result and wait for the
second conversion which will be fully-settled.
FIGURE 9. Analog Input Change Timing.
Begin New Conversion,
Complete Previous Conversion
New Conversion Complete
t
DELAY
DRDY/DOUT
V
IN
Previous Conversion Data
FIGURE 10. Settling Error vs Delay Time.
SETTLING ERROR vs DELAY TIME
f
CLK = 2.4576MHz
Delay Time, t
DELAY (ms)
Settling
Error
(%)
2
4
6
8
10
12
14
16
0
10.000000
1.000000
0.100000
0.010000
0.001000
0.000100
0.000010
0.000001
FIGURE 7. Frequency Response to 180Hz.
FIGURE 8. Frequency Response Near 50Hz and 60Hz.
FREQUENCY RESPONSE TO 180Hz
f
CLK = 2.4576MHz
Frequency (Hz)
Gain
(dB)
0
10
20
30
40
50
60
70
80
90
100
11
0
120
130
140
150
160
170
180
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
FREQUENCY RESPONSE NEAR 50Hz AND 60Hz
f
CLK = 2.4576MHz
Frequency (Hz)
Gain
(dB)
50
55
60
65
45
–40
–50
–60
–70
–80
–90
–100
–110
–120
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