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参数资料
| 型号： | ADS1252U/2K5 |
| 元件分类： | ADC |
| 英文描述： | 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO8 |
| 封装： | SO-8 |
| 文件页数： | 14/14页 |
| 文件大小： | 131K |
| 代理商： | ADS1252U/2K5 |
9
ADS1252
clock (CLK) (modulator clock = CLK
÷ 6), the number of
system clocks required for the digital filter to fully settle is
5 64 6, or 1920 CLKs. This means that any significant
step change at the analog input requires five full conversions
to settle. However, if the analog input change occurs asyn-
chronously to the DOUT/DRDY pulse, six conversions are
required to ensure full settling.
CONTROL LOGIC
The control logic is used for communications and control of
the ADS1252.
Power-Up Sequence
Prior to power-up, all digital and analog input pins must be
LOW. At the time of power-up, these signal inputs can be
biased to a voltage other than 0V, however, they should
never exceed +VD.
Once the ADS1252 powers up, the DOUT/DRDY line will
pulse LOW on the first conversion. This data will not be
valid. The sixth pulse of DOUT/DRDY will be valid data
from the analog input signal.
DOUT/DRDY
The DOUT/DRDY output signal alternates between two
modes of operation. The first mode of operation is the Data
Ready mode (DRDY) to indicate that new data has been
loaded into the data output register and is ready to be read.
The second mode of operation is the Data Output (DOUT)
mode and is used to serially shift data out of the Data Output
Register (DOR). The time domain partitioning of the DRDY
and DOUT function is shown in Figure 11.
The basic timing for DOUT/DRDY is shown in Figure 12.
During the time defined by t2, t3, and t4, the DOUT/DRDY
pin functions in DRDY mode. The state of the
DOUT/DRDY pin would be HIGH prior to the internal
transfer of new data to the DOR. The result of the A/D
conversion would be written to the DOR from MSB to LSB
in the time defined by t1 (see Figures 11 and 12). The
DOUT/DRDY line would then pulse LOW for the time
defined by t2, and then pulse HIGH for the time defined by
t3 to indicate that new data was available to be read. At this
point, the function of the DOUT/DRDY pin would change
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tDRDY
Conversion Cycle
384 CLK
ns
DRDY Mode
36 CLK
ns
DOUT Mode
348 CLK
ns
t1
DOR Write Time
6 CLK
ns
t2
DOUT/DRDY LOW Time
6 CLK
ns
t3
DOUT/DRDY HIGH Time (Prior to Data Out)
6 CLK
ns
t4
DOUT/DRDY HIGH Time (Prior to Data Ready)
24 CLK
ns
t5
Rising Edge of CLK to Falling Edge of DOUT/DRDY
30
ns
t6
End of DRDY Mode to Rising Edge of First SCLK
30
ns
t7
End of DRDY Mode to Data Valid (Propogation Delay)
30
ns
t8
Falling Edge of SCLK to Data Valid (Hold Time)
5
ns
t9
Falling Edge of SCLK to Next Data Out Valid (Propogation Delay)
30
ns
t10
SCLK Setup Time for Synchronization or Power Down
30
ns
t11
DOUT/DRDY Pulse for Synchronization or Power Down
3 CLK
ns
t12
Rising Edge of SCLK Until Start of Synchronization
1537 CLK
7679 CLK
ns
t13
Synchronization Time
0.5 CLK
6143.5 CLK
ns
t14
Falling Edge of CLK (After SCLK Goes Low) Until Start of DRDY Mode
314.5 CLK
ns
t15
Rising Edge of SCLK Until Start of Power Down
7681 CLK
ns
t16
Falling Edge of CLK (After SCLK Goes Low) Until Start of DRDY Mode
591.5 CLK
592.5 CLK
ns
t17
Falling Edge of Last DOUT/DRDY to Start of Power Down
6143.5 CLK
ns
TABLE II. Digital Timing.
FIGURE 9. Expanded Digital Filter Response (60Hz with a
60Hz Notch).
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
56
57
58
59
60
61
62
63
64
65
55
Frequency (Hz)
Gain
(dB)
FIGURE 10. Expanded Digital Filter Response (60Hz with
a 10Hz Notch).
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
56
57
58
59
60
61
62
63
64
65
55
Frequency (Hz)
Gain
(dB)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADS1252UG4 | 功能描述:模数转换器 - ADC ResolutionPlus 24-Bit 40kHz RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ADS1253 | 制造商:TI 制造商全称:Texas Instruments 功能描述:24-Bit, 20kHz, Low Power ANALOG-TO-DIGITAL CONVERTER |
| ADS1253E | 功能描述:模数转换器 - ADC 24-Bit 20kHz Low Power RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ADS1253E/2K5 | 功能描述:模数转换器 - ADC 24-Bit 20kHz Low Power RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ADS1253E/2K5G4 | 功能描述:模数转换器 - ADC 24-Bit 20kHz Low Power RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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