参数资料
型号: ADS1252U/2K5
元件分类: ADC
英文描述: 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO8
封装: SO-8
文件页数: 4/14页
文件大小: 131K
代理商: ADS1252U/2K5
12
ADS1252
A simple two-wire interface is shown in Figure 15. Essentially
P3.2 (INT
0) generates an internal interrupt when DOUT/
DRDY pulses LOW. The user firmware in the 8xC51 vectors
to the interupt handler and shifts the data in using P3.1 as
SCLK and P3.2 as data in. The P1.0 output from 8xC51 is a
free-running clock.
The data must be clocked out before the ADS1252 enters
DRDY mode to ensure reception of valid data, as described
in the DOUT/DRDY section of this data sheet.
ISOLATION
The serial interface of the ADS1252 provides for simple
isolation methods. An example of an isolated three-wire
interface is shown in Figure 16. The ISO150 is used to
transmit the digital clocks over the isolation barrier. In
addition, the digital output of the ADS1252 can, in some
cases, drive opto-isolators directly.
FIGURE 15. Two-Wire Interface to an 8xC51.
+V
IN
–V
IN
+V
DD
CLK
V
REF
GND
SCLK
DOUT/DRDY
V
REF
Circuit
DV
DD
8xC51
ADS1252
P1.0/T2
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0
P3.1
P3.2 (INT0)
P3.3
P3.4
P3.5
P3.6
P3.7
XTAL2
XTAL1
V
SS
V
CC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
EA
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
V
S
DGND
C1
XTAL
C2
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