参数资料
型号: ADS8412IBPFBTG4
厂商: TEXAS INSTRUMENTS INC
元件分类: ADC
英文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48
封装: GREEN, PLASTIC, TQFP-48
文件页数: 13/29页
文件大小: 1018K
代理商: ADS8412IBPFBTG4
www.ti.com
PRINCIPLES OF OPERATION
REFERENCE
ANALOG INPUT
ADS8412
SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
The ADS8412 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The
architecture is based on charge redistribution, which inherently includes a sample/hold function. See Figure 29
for the application circuit for the ADS8412.
The conversion clock is generated internally. The conversion time of 400 ns is capable of sustaining a 2-MHz
throughput.
The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input
on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are
disconnected from any internal function.
The ADS8412 can operate with an external reference with a range from 3.9 V to 4.2 V. A 4.096-V internal
reference is included. When internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN)
with an 0.1 F decoupling capacitor and 1 F storage capacitor between pin 2 (REFOUT) and pins 47 and 48
(REFM) (see Figure 33). The internal reference of the converter is double buffered. If an external reference is
used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also
used to recharge all of the capacitors of the CDAC during conversion. Pin 2 (REFOUT) can be left unconnected
(floating) if external reference is used.
When the converter enters the hold mode, the voltage difference between the +IN and -IN inputs is captured on
the internal capacitor array. Both +IN and -IN input has a range of –0.2 V to Vref + 0.2 V. The input span(+IN –
(–IN)) is limited to –Vref to Vref.
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source
impedance. Essentially, the current into the ADS8412 charges the internal capacitor array during the sample
period. After this capacitance has been fully charged, there is no further input current. The source of the analog
input voltage must be able to charge the input capacitance (25 pF) to an 16-bit settling level within the acquisition
time (100 ns) of the device. When the converter goes into the hold mode, the input impedance is greater than 1
G
.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the
+IN and –IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, the
converter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass
filters should be used.
Care should be taken to ensure that the output impedance of the sources driving +IN and –IN inputs are
matched. If this is not observed, the two inputs could have different setting time. This may result in offset error,
gain error and linearity error which varies with temperature and input voltage.
A typical input circuit using TI's THS4503 is shown Figure 31. Input from a single-ended source may be
converted into differential signal for ADS8412 as shown in the figure. In case the source itself is differential then
THS4503 may be used in differential input and differential output mode.
20
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