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参数资料
| 型号： | ADS8517IPWR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDSO28 |
| 封装： | GREEN, PLASTIC, TSSOP-28 |
| 文件页数： | 34/38页 |
| 文件大小： | 948K |
| 代理商： | ADS8517IPWR |
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PIN CONFIGURATION
V
DIG
V
ANA
BUSY
CS
R/C
BYTE
TAG
SDATA
DATACLK
D0
D1
D2
R1
IN
AGND1
CAP
REF
AGND2
D7
D6
D5
D4
D3
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS8517
R2
IN
SB/BTC
EXT/INT
REFD
PWRD
www.ti.com ................................................................................................................................................. SLAS527A – SEPTEMBER 2008 – REVISED JUNE 2009
DW, PW PACKAGES
SO-28, TSSOP-28
(TOP VIEW)
PIN ASSIGNMENTS
PIN
DIGITAL
NAME
NO.
I/O
DESCRIPTION
R1IN
1
Analog Input.
AGND1
2
Analog sense ground. Used internally as ground reference point. Minimal current flow
R2IN
3
Analog Input.
CAP
4
Reference buffer output. 2.2-
F tantalum capacitor to ground.
Reference input/output. Outputs internal 2.5-V reference. Can also be driven by external system
REF
5
reference. In both cases, bypass to ground with a 2.2-
F tantalum capacitor.
AGND2
6
Analog ground
Output mode select. Selects straight binary or binary twos complement for output data format. If
SB/BTC
7
I
high, data are output in a straight binary format. If low, data are output in a binary twos
complement format.
External/internal data select. Selects external/internal data clock for transmitting data. If high,
data is output synchronized to the clock input on DATACLK. If low, a convert command initiates
EXT/INT
8
I
the transmission of the data from the previous conversion, along with 16-clock pulses output on
DATACLK.
Data bit 7 if BYTE is high. Data bit 15 (MSB) if BYTE is low. High-Z when CS is high and/or R/C
D7
9
O
is low. Leave unconnected when using serial output.
D6
10
O
Data bit 6 if BYTE is high. Data bit 14 if BYTE is low. High-Z when CS is high and/or R/C is low.
D5
11
O
Data bit 5 if BYTE is high. Data bit 13 if BYTE is low. High-Z when CS is high and/or R/C is low.
D4
12
O
Data bit 4 if BYTE is high. Data bit 12 if BYTE is low. High-Z when CS is high and/or R/C is low.
D3
13
O
Data bit 3 if BYTE is high. Data bit 11 if BYTE is low. High-Z when CS is high and/or R/C is low.
DGND
14
Digital ground
D2
15
O
Data bit 2 if BYTE is high. Data bit 10 if BYTE is low. High-Z when CS is high and/or R/C is low.
D1
16
O
Data bit 1 if BYTE is high. Data bit 9 if BYTE is low. High-Z when CS is high and/or R/C is low.
Data bit 0 (LSB) if BYTE is high. Data bit 8 if BYTE is low. High-Z when CS is high and/or R/C is
D0
17
O
low.
Copyright 2008–2009, Texas Instruments Incorporated
5
Product Folder Link(s): ADS8517
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