参数资料
型号: ADSP-2105BP-80
厂商: Analog Devices Inc
文件页数: 20/64页
文件大小: 0K
描述: IC DSP CONTROLLER 16BIT 68PLCC
标准包装: 19
系列: ADSP-21xx
类型: 定点
接口: 同步串行端口(SSP)
时钟速率: 20MHz
非易失内存: 外部
芯片上RAM: 3kB
电压 - 输入/输出: 5.00V
电压 - 核心: 5.00V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 68-LCC(J 形引线)
供应商设备封装: 68-PLCC(24.23x24.23)
包装: 管件
ADSP-21xx
REV. B
–27–
POWER DISSIPATION EXAMPLE
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C
× V
DD
2
× f
C = load capacitance, f = output switching frequency.
Example:
In an ADSP-2103 application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:
Assumptions:
External data memory is accessed every cycle with 50% of the
address pins switching.
External data memory writes occur every other cycle with
50% of the data pins switching.
Each address and data pin has a 10 pF total load at the pin.
The application operates at V
DD = 3.3 V and tCK = 100 ns.
Total Power Dissipation = PINT + (C
× V
DD
2
× f )
PINT = internal power dissipation (from Figure 23).
(C
× V
DD
2
× f ) is calculated for each output:
# of
Output
Pins
× C
× V
DD
2
× f
Address, DMS 8
× 10 pF × 3.32 V × 10 MHz = 8.71 mW
Data, WR
9
× 10 pF × 3.32 V × 5 MHz = 4.90 mW
RD
1
× 10 pF × 3.32 V × 5 MHz = 0.55 mW
CLKOUT
1
× 10 pF × 3.32 V × 10 MHz = 1.09 mW
15.25 mW
Total power dissipation for this example = PINT + 15.25 mW.
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
TAMB = TCASE – (PD × θCA)
TCASE = Case Temperature in
°C
PD = Power Dissipation in W
θ
CA = Thermal Resistance (Case-to-Ambient)
θ
JA = Thermal Resistance (Junction-to-Ambient)
θ
JC = Thermal Resistance (Junction-to-Case)
Package
θ
JA
θ
JC
θ
CA
PGA
27
°C/W
16
°C/W
11
°C/W
PQFP
60
°C/W
18
°C/W
42
°C/W
SPECIFICATIONS (ADSP-2103/2162/2164)
Figure 25. Typical Output Valid Delay or Hold vs. Load
Capacitance, C
L (at Maximum Ambient Operating Temperature)
Figure 24. Typical Output Rise Time vs. Load Capacitance, C
L
(at Maximum Ambient Operating Temperature)
CAPACITIVE LOADING
Figures 24 and 25 show capacitive loading characteristics for the
ADSP-2103, ADSP-2162, and ADSP-2164.
25
150
125
100
75
CL – pF
50
RISE
TIME
(0.8V-2.0V)
ns
30
10
5
15
20
25
VDD = 3.0V
VALID
OUTPUT
DELAY
OR
HOLD
ns
–2
+4
+2
+6
NOMINAL
25
150
125
100
75
C L – pF
50
+8
VDD = 3.0V
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