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| 型号： | ADSP-21060CW-160 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 42/64页 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 240CQFP |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | 主机接口，连接端口，串行端口 |
| 时钟速率： | 40MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 512kB |
| 电压 - 输入/输出： | 5.00V |
| 电压 - 核心： | 5.00V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 240-CBFQFP 裸露焊盘 |
| 供应商设备封装： | 240-CQFP（32x32） |
| 包装： | 托盘 |
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Rev. F
|
Page 47 of 64
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March 2008
TEST CONDITIONS
For the ac signal specifications (timing parameters), see Timing
Specifications on Page 21. These specifications include output
disable time, output enable time, and capacitive loading. The
timing specifications for the DSP apply for the voltage reference
levels in Figure 28.
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by
'V is dependent on the capacitive load, C
L, and the
load current, IL. This decay time can be approximated by the fol-
lowing equation:
The output disable time tDIS is the difference between
the interval from when the reference signal switches to when the
output voltage decays
'V from the measured output high or
output low voltage. tDECAY is calculated with test loads CL and IL,
and with
'V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The output enable time tENA is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 29). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose
'V
to be the difference between the ADSP-2106x’s output voltage
and the input threshold for the device requiring the hold time. A
typical
'V will be 0.4 V. C
L is the total bus capacitance (per data
line), and IL is the total leakage or three-state current (per data
line). The hold time will be tDECAY plus the minimum disable
time (i.e., tDATRWH for the write cycle).
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 30). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figure 32,
graphically how output delays and holds vary with load capaci-
tance. (Note that this graph or derating does not apply to output
disable delays; see the previous section Output Disable Time
shown.
Output Drive Characteristics
Figure 31 shows typical I-V characteristics for the output driv-
ers of the ADSP-2106x. The curves represent the current drive
capability of the output drivers as a function of output voltage.
Figure 28. Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
Figure 29. Output Enable/Disable
INPUT
OR
OUTPUT
1.5V
PEXT
CL V
'
IL
--------------
=
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS
DRIVING
VOH (MEASURED) - V
VOL (MEASURED) + V
tMEASURED
VOH (MEASURED)
VOL (MEASURED)
2.0V
1.0V
VOH (MEASURED)
VOL (MEASURED)
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
tENA
tDECAY
Figure 30. Equivalent Device Loading for AC Measurements (Includes All
Fixtures)
+1.5V
50pF
TO
OUTPUT
PIN
IOL
IOH
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相关代理商/技术参数 |
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| ADSP-21060CWZ-133 | 制造商:Analog Devices 功能描述:DSP FLOATING PT 32BIT 33MHZ 240CQFP - Trays |
| ADSP-21060CWZ-160 | 制造商:Analog Devices 功能描述:DSP FLOATING PT 32BIT 40MHZ 40MIPS 240CQFP - Trays |
| ADSP-21060CZ-133 | 功能描述:IC DSP CONTROLLER 32BIT 240CQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21060CZ-160 | 功能描述:IC DSP CONTROLLER 32BIT 240CQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21060CZ-160 | 制造商:Analog Devices 功能描述:Digital Signal Processor IC Supply Volta |
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