参数资料
型号: ADSP-21363KBCZ-1AA
厂商: Analog Devices Inc
文件页数: 38/60页
文件大小: 0K
描述: IC DSP 32BIT 333MHZ 136-CSPBGA
产品培训模块: SHARC Processor Overview
标准包装: 1
系列: SHARC®
类型: 浮点
接口: DAI,SPI
时钟速率: 333MHz
非易失内存: ROM(512 kB)
芯片上RAM: 384kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 136-LFBGA,CSPBGA
供应商设备封装: 136-CSPBGA(12x12)
包装: 托盘
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left justified, I 2 S, or right justified with word widths of 16-, 18-,
20-, or 24-bits. The following sections provide timing for the
transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 29 shows the right-justified mode. Frame sync is high for
the left channel and low for the right channel. Data is valid on
the rising edge of serial clock. The MSB is delayed the minimum
in 24-bit output mode or the maximum in 16-bit output mode
from a frame sync transition, so that when there are 64 serial
clock periods per frame sync period, the LSB of the data is right-
justified to the next frame sync transition.
Table 33. S/PDIF Transmitter Right-Justified Mode
Parameter
Timing Requirement
t RJD
FS to MSB Delay in Right-Justified Mode
Nominal
Unit
DAI_P20–1
FS
DAI_P20–1
SCLK
16-Bit Word Mode
18-Bit Word Mode
20-Bit Word Mode
24-Bit Word Mode
t RJD
LEFT/RIGHT CHANNEL
16
14
12
8
SCLK
SCLK
SCLK
SCLK
DAI_P20–1
SDATA
LSB
MSB
MSB–1
MSB–2
LSB+2
LSB+1
LSB
Figure 29. Right-Justified Mode
Rev. J |
Page 38 of 60 |
July 2013
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