参数资料
型号: ADSP-21375BSWZ-2B
厂商: Analog Devices Inc
文件页数: 14/56页
文件大小: 0K
描述: IC DSP 32BIT 266MHZ 208-MQFP
产品培训模块: SHARC Processor Overview
标准包装: 36
系列: SHARC®
类型: 浮点
接口: DAI,DPI
时钟速率: 266MHz
非易失内存: ROM(256 kB)
芯片上RAM: 64kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 208-LQFP 裸露焊盘
供应商设备封装: 208-LQFP-EP(28x28)
包装: 托盘
Table 9. Pin Descriptions (Continued)
State During
and After
Name
SDCKE
SDA10
SDCLK
MS 0–1
Type
O/T (pu)
O/T (pu)
O/T
O/T (pu)
Reset
Pulled high/
driven high
Pulled high/
driven low
High-Z/driving
Pulled high/
driven high
Description
SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK
signal. For details, see the data sheet supplied with the SDRAM device.
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a non-
SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.
SDRAM Clock.
Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-
sponding banks of external memory. The MS 1-0 lines are decoded memory address lines
that change at the same time as the other address lines. The MS1 pin can be used in
EPORT/FLASH boot mode. For more information, see the ADSP-2137x SHARC Processor
Hardware Reference.
FLAG[0]/IRQ0
FLAG[1]/IRQ1
FLAG[2]/IRQ2/
MS2
I/O
I/O
I/O with
programmable pu
FLAG[0] INPUT
FLAG[1] INPUT
FLAG[2] INPUT
FLAG0/Interrupt Request0.
FLAG1/Interrupt Request1.
FLAG2/Interrupt Request/Memory Select2.
(for MS mode)
FLAG[3]/
TMREXP/ MS3
I/O with
programmable pu
FLAG[3] INPUT
FLAG3/Timer Expired/Memory Select3.
(for MS mode)
TDI
TDO
TMS
TCK
TRST
EMU
CLK_CFG 1–0
BOOT_CFG 1–0
I (pu)
O/T
I (pu)
I
I (pu)
O (O/D) (pu)
I
I
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 k ? internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 k ?
internal pull-up resistor.
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the processor.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the processor. TRST has a 22.5 k ?
internal pull-up resistor.
Emulation Status. Must be connected to the processor. Analog Devices DSP Tools
product line of JTAG emulators target board connector only. EMU has a 22.5 k ? internal
pull-up resistor.
Core to CLKIN Ratio Control. These pins set the start up clock frequency. See the
ADSP-2137x SHARC Processor Hardware Reference for a description of the clock configu-
ration modes.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset.
Boot Configuration Select. These pins select the boot mode for the processor. The
BOOT_CFG pins must be valid before reset is asserted. See the ADSP-2137x SHARC
Processor Hardware Reference for information about boot modes.
Rev. D | Page 14 of 56 | April 2013
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