参数资料
型号: ADSP-21990BSTZ
厂商: Analog Devices Inc
文件页数: 18/50页
文件大小: 0K
描述: IC DSP CONTROLLER 16BIT 176-LQFP
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 1
系列: ADSP-21xx
类型: 定点
接口: SPI,SSP
时钟速率: 160MHz
非易失内存: 外部
芯片上RAM: 20kB
电压 - 输入/输出: 3.30V
电压 - 核心: 2.50V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 176-LQFP
供应商设备封装: 176-LQFP(24x24)
包装: 托盘
ADSP-21990
Rev. A
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Page 25 of 50
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August 2007
Clock In and Clock Out Cycle Timing
Table 6 and Figure 7 describe clock and reset operations. Com-
binations of CLKIN and clock multipliers must not select
core/peripheral clocks in excess of 160 MHz/80 MHz for the
ADSP-21990BST and 150 MHz/75 MHz for the
ADSP-21990BBC, when the peripheral clock rate is one-half the
core clock rate. If the peripheral clock rate is equal to the core
clock rate, the maximum peripheral clock rate is 80 MHz for the
ADSP-21990BST and 75 MHz for the ADSP-21990BBC. The
peripheral clock is supplied to the CLKOUT pins.
When changing from bypass mode to PLL mode, allow 512
HCLK cycles for the PLL to stabilize.
Table 6. Clock In and Clock Out Cycle Timing
Parameter
Min
Max
Unit
Timing Requirements
tCK
CLKIN Period1, 2
10
200
ns
tCKL
CLKIN Low Pulse
4.5
ns
tCKH
CLKIN High Pulse
4.5
ns
tWRST
RESET Asserted Pulse Width Low
200tCLKOUT
ns
tMSS
MSELx/BYPASS Stable Before RESET Deasserted Setup
40
μs
tMSH
MSELx/BYPASS Stable After RESET Deasserted Hold
1000
ns
tMSD
MSELx/BYPASS Stable After RESET Asserted
200
ns
tPFD
Flag Output Disable Time After RESET Asserted
10
ns
Switching Characteristics
tCKOD
CLKOUT Delay from CLKIN
0
5.8
ns
tCKO
CLKOUT Period3
12.5
ns
1 In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN = CCLK), tCK = tCCLK.
2 In bypass mode, tCK = tCCLK.
3 CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.
Figure 7. Clock In and Clock Out Cycle Timing
tCKOD
CLKOUT
MSEL6–0
BYPASS
DF
RESET
CLKIN
tWRST
tCKH
tCK
tCKL
tMSH
tCKO
tPFD
tMSD
tMSS
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