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| 型号： | ADSP-BF561SBBZ500 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/64页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR 500MHZ 297-PBGA |
| 产品培训模块： | Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services |
| 标准包装： | 1 |
| 系列： | Blackfin® |
| 类型： | 定点 |
| 接口： | SPI，SSP，UART |
| 时钟速率： | 500MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 328kB |
| 电压 - 输入/输出： | 2.50V，3.30V |
| 电压 - 核心： | 1.25V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 297-BGA |
| 供应商设备封装： | 297-PBGA（27x27） |
| 包装： | 托盘 |
| 配用： | ADZS-BFAUDIO-EZEXT-ND - BOARD EVAL AUDIO BLACKFIN ADZS-BF561-EZLITE-ND - BOARD EVAL ADSP-BF561 ADZS-BF561-MMSKIT-ND - KIT STARTER MULTIMEDIA BF561 ADZS-BFAV-EZEXT-ND - BOARD DAUGHT ADSP-BF533,37,61KIT |
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ADSP-BF561
ADDRESS ARITHMETIC UNIT
SP
I3
I2
L3
L2
B3
B2
M3
M2
FP
P5
I1
I0
L1
L0
B1
B0
M1
M0
DAG1
DAG0
P4
P3
DA1
DA0
SD
32
32
32
32
RAB
P2
P1
P0
32
PREG
LD1
LD0
32
32
32
32
ASTAT
SEQUENCER
R7.H
R6.H
R7.L
R6.L
R5.H
R4.H
R3.H
R5.L
R4.L
R3.L
8
16
8
8
16
8
ALIGN
R2.H
R1.H
R2.L
R1.L
BARREL
DECODE
R0.H
R0.L
SHIFTER
A0
40
40
40
40
A1
LOOP BUFFER
CONTROL
UNIT
32
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
MEMORY ARCHITECTURE
The ADSP-BF561 views memory as a single unified 4G byte
address space, using 32-bit addresses. All resources including
internal memory, external memory, and I/O control registers
occupy separate sections of this common address space. The
memory portions of this address space are arranged in a hierar-
chical structure to provide a good cost/performance balance of
some very fast, low latency memory as cache or SRAM very
close to the processor, and larger, lower cost and performance
memory systems farther away from the processor. The
The L1 memory system in each core is the highest performance
memory available to each Blackfin core. The L2 memory pro-
vides additional capacity with lower performance. Lastly, the
off-chip memory system, accessed through the External Bus
Interface Unit (EBIU), provides expansion with SDRAM, flash
memory, and SRAM, optionally accessing more than
768M bytes of physical memory. The memory DMA controllers
provide high bandwidth data movement capability. They can
perform block transfers of code or data between the internal
L1/L2 memories and the external memory spaces.
Internal (On-Chip) Memory
The ADSP-BF561 has four blocks of on-chip memory providing
high bandwidth access to the core.
The first is the L1 instruction memory of each Blackfin core
consisting of 16K bytes of four-way set-associative cache mem-
ory and 16K bytes of SRAM. The cache memory may also be
configured as an SRAM. This memory is accessed at full proces-
sor speed. When configured as SRAM, each of the two 16K
banks of memory is broken into 4K sub-banks which can be
independently accessed by the processor and DMA.
The second on-chip memory block is the L1 data memory of
each Blackfin core which consists of four banks of 16K bytes
each. Two of the L1 data memory banks can be configured as
one way of a two-way set-associative cache or as an SRAM. The
other two banks are configured as SRAM. All banks are accessed
at full processor speed. When configured as SRAM, each of the
four 16K banks of memory is broken into 4K sub-banks which
can be independently accessed by the processor and DMA.
The third memory block associated with each core is a 4K byte
scratchpad SRAM which runs at the same speed as the L1 mem-
ories, but is only accessible as data SRAM (it cannot be
configured as cache memory and is not accessible via DMA).
Rev. E |
Page 4 of 64 |
September 2009
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-BF561SBBZ600 | 功能描述:IC DSP 32BIT 600MHZ 297-BGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF561SBBZ600 | 制造商:Analog Devices 功能描述:Digital Signal Processor IC |
| ADSPBF561SBBZC70.3 | 制造商:Analog Devices 功能描述: |
| ADSP-BF561SBBZ-ENG | 制造商:Analog Devices 功能描述:ENG SAMPLES - Trays |
| ADSP-BF561SKB500 | 功能描述:IC DSP CTRLR 32BIT 500MHZ 297BGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
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