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| 型号： | ADSP-TS201SABPZ060 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/48页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR 600MHZ 576BGA |
| 标准包装： | 1 |
| 系列： | TigerSHARC® |
| 类型： | 定点/浮点 |
| 接口： | 主机接口，连接端口，多处理器 |
| 时钟速率： | 600MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 3MB |
| 电压 - 输入/输出： | 2.50V |
| 电压 - 核心： | 1.20V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 576-BBGA 裸露焊盘 |
| 供应商设备封装： | 576-BGA-ED（25x25） |
| 包装： | 托盘 |
| 配用： | ADZS-TS201S-EZLITE-ND - KIT LITE EVAL FOR ADSP-TS201S |
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Rev. C
|
Page 14 of 48
|
December 2006
ADSP-TS201S
Table 6. Pin Definitions—External Port Arbitration
Signal
Type
Term
Description
BR7–0
I/O
VDD_IO
1
Multiprocessing Bus Request Pins. Used by the DSPs in a multiprocessor system to
arbitrate for bus mastership. Each DSP drives its own BRx line (corresponding to the
value of its ID2–0 inputs) and monitors all others. In systems with fewer than eight
DSPs, set the unused BRx pins high (VDD_IO).
ID2–0
I (pd)
na
Multiprocessor ID. Indicates the DSP’s ID, from which the DSP determines its order in
a multiprocessor system. These pins also indicate to the DSP which bus request
(BR0–BR7) to assert when requesting the bus: 000 = BR0, 001 = BR1, 010 = BR2,
011 = BR3, 100 = BR4, 101 = BR5, 110 = BR6, or 111 = BR7. ID2–0 must have a
constant value during system operation and can change during reset only.
BM
O
na
Bus Master. The current bus master DSP asserts BM. For debugging only. At reset this
is a strap pin. For more information, see Table 16 on Page 20.
BOFF
I
epu
Back Off. A deadlock situation can occur when the host and a DSP try to read from
each other’s bus at the same time. When deadlock occurs, the host can assert BOFF
to force the DSP to relinquish the bus before completing its outstanding transaction.
BUSLOCK
O/T
(pu_0)
na
Bus Lock Indication. Provides an indication that the current bus master has locked the
bus. At reset, this is a strap pin. For more information, see Table 16 on Page 20.
HBR
I
epu
Host Bus Request. A host must assert HBR to request control of the DSP’s external bus.
When HBR is asserted in a multiprocessing system, the bus master relinquishes the
bus and asserts HBG once the outstanding transaction is finished.
HBG
I/O/T
(pu_0)
epu2
Host Bus Grant. Acknowledges HBR and indicates that the host can take control of
the external bus. When relinquishing the bus, the master DSP three-states the
ADDR31–0, DATA63–0, MSH, MSSD3–0, MS1–0, RD, WRL, WRH, BMS, BRST, IORD,
IOWR, IOEN, RAS, CAS, SDWE, SDA10, SDCKE, LDQM, and HDQM pins, and the DSP
puts the SDRAM in self-refresh mode. The DSP asserts HBG until the host deasserts
HBR. In multiprocessor systems, the current bus master DSP drives HBG, and all slave
DSPs monitor it.
CPA
I/O/OD
(pu_od_0)
epu2
Core Priority Access. Asserted while the DSP’s core accesses external memory. This
pin enables a slave DSP to interrupt a master DSP’s background DMA transfers and
gain control of the external bus for core-initiated transactions. CPA is an open drain
output, connected to all DSPs in the system. If not required in the system, leave CPA
unconnected (external pull-ups will be required for DSP ID = 1 through ID = 7).
DPA
I/O/OD
(pu_od_0)
epu2
DMA Priority Access. Asserted while a high priority DSP DMA channel accesses
external memory. This pin enables a high priority DMA channel on a slave DSP to
interrupt transfers of a normal priority DMA channel on a master DSP and gain control
of the external bus for DMA-initiated transactions. DPA is an open drain output,
connected to all DSPs in the system. If not required in the system, leave DPA uncon-
nected (external pull-ups will be required for DSP ID = 1 through ID = 7).
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k
Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
pull-up 500
Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
= internal pull-up 40 k
Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
Ω to VSS; epu = external pull-up approx-
imately 5 k
Ω to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS
1 The BRx pin matching the ID2–0 input selection for the processor should be left nc if unused. For example, the processor with ID = 000 has BR0 = nc and BR7–1 = V
DD_IO.
2 This external pull-up resistor may be omitted for the ID = 000 TigerSHARC processor.
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