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参数资料
| 型号： | ADSP-TS202SABPZ050 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/48页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR 500MHZ 576BGA |
| 标准包装： | 1 |
| 系列： | TigerSHARC® |
| 类型： | 定点/浮点 |
| 接口： | 主机接口，连接端口，多处理器 |
| 时钟速率： | 500MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 1.5MB |
| 电压 - 输入/输出： | 2.50V |
| 电压 - 核心： | 1.05V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 576-BBGA 裸露焊盘 |
| 供应商设备封装： | 576-BGA-ED（25x25） |
| 包装： | 托盘 |
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Rev. C
|
Page 10 of 48
|
December 2006
ADSP-TS202S
POWER DOMAINS
The ADSP-TS202S processor has separate power supply con-
nections for internal logic (VDD), analog circuits (VDD_A), I/O
buffer (VDD_IO), and internal DRAM (VDD_DRAM) power supply.
Note that the analog (VDD_A) supply powers the clock generator
PLLs. To produce a stable clock, systems must provide a clean
power supply to power input VDD_A. Designs must pay critical
attention to bypassing the VDD_A supply.
FILTERING REFERENCE VOLTAGE AND CLOCKS
and SCLK_VREF. These circuits provide the reference voltages
for the switching voltage reference and system clock reference.
DEVELOPMENT TOOLS
The ADSP-TS202S processor is supported with a complete set
of CROSSCORE
software and hardware development tools,
including Analog Devices emulators and VisualDSP++
devel-
opment environment. The same emulator hardware that
supports other TigerSHARC processors also fully emulates the
ADSP-TS202S processor.
The VisualDSP++ project management environment lets
programmers develop and debug an application. This environ-
ment includes an easy to use assembler (which is based on an
algebraic syntax), an archiver (librarian/library builder), a
linker, a loader, a cycle-accurate instruction-level simulator, a
C/C++ compiler, and a C/C++ run-time library that includes
DSP and mathematical functions. A key point for theses tools is
C/C++ code efficiency. The compiler has been developed for
efficient translation of C/C++ code to DSP assembly. The DSP
has architectural features that improve the efficiency of
compiled C/C++ code.
The VisualDSP++ debugger has a number of important
features. Data visualization is enhanced by a plotting package
that offers a significant level of flexibility. This graphical repre-
sentation of user data enables the programmer to quickly
determine the performance of an algorithm. As algorithms grow
in complexity, this capability can have increasing significance
on the designer’s development schedule, increasing
productivity. Statistical profiling enables the programmer to
nonintrusively poll the processor as it is running the program.
This feature, unique to VisualDSP++, enables the software
developer to passively gather important code execution metrics
without interrupting the real-time characteristics of the
program. Essentially, the developer can identify bottlenecks in
software quickly and efficiently. By using the profiler, the pro-
grammer can focus on those areas in the program that impact
performance and take corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can
View mixed C/C++ and assembly code (interleaved source
and object information)
Insert breakpoints
Set conditional breakpoints on registers, memory,
and stacks
Trace instruction execution
Perform linear or statistical profiling of program execution
Fill, dump, and graphically plot the contents of memory
Perform source level debugging
Create custom debugger windows
The VisualDSP++ IDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the TigerSHARC
processor development tools, including the color syntax high-
lighting in the VisualDSP++ editor. This capability permits
programmers to
Control how the development tools process inputs and
generate outputs
Maintain a one-to-one correspondence with the tool’s
command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
Figure 6. VREF Filtering Scheme
Figure 7. SCLK_VREF Filtering Scheme
CROSSCORE is a registered trademark of Analog Devices, Inc.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
VDD_IO
VSS
VREF
R1
R2
C1
C2
R1: 2k
SERIES RESISTOR (±1%)
R2: 2.55k
SERIES RESISTOR (±1%)
C1: 1 F CAPACITOR (SMD)
C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS
CLOCK DRIVER
VOLTAGE OR
VDD_IO
VSS
SCLK_VREF
R1
R2
C1
C2
R1: 2k
SERIES RESISTOR (±1%)
R2: 2.55k
SERIES RESISTOR (±1%)
C1: 1 F CAPACITOR (SMD)
C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS
*IF CLOCK DRIVER VOLTAGE > V
DD_IO
*
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-TS203SABP-050 | 功能描述:IC DSP FLOAT/FIXED 500MHZ 576BGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:TigerSHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-TS203SABP-05X | 制造商:Analog Devices 功能描述: |
| ADSP-TS203SABPZ050 | 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:TigerSHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-TS203SBBPZ050 | 制造商:Analog Devices 功能描述:DSP - Bulk |
| ADSQ-1410 | 制造商:MURATA-PS 制造商全称:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
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