ADSP-TS202SABPZ050 (Analog) PDF资料下载 Datasheet(8/48 页)

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型号：	ADSP-TS202SABPZ050
厂商：	Analog Devices Inc
文件页数：	8/48页
文件大小：	0K
描述：	IC PROCESSOR 500MHZ 576BGA
标准包装：	1
系列：	TigerSHARC®
类型：	定点/浮点
接口：	主机接口，连接端口，多处理器
时钟速率：	500MHz
非易失内存：	外部
芯片上RAM：	1.5MB
电压 - 输入/输出：	2.50V
电压 - 核心：	1.05V
工作温度：	-40°C ~ 85°C
安装类型：	表面贴装
封装/外壳：	576-BBGA 裸露焊盘
供应商设备封装：	576-BGA-ED（25x25）
包装：	托盘

Rev. C

Page 16 of 48

December 2006

ADSP-TS202S

SDA10

O/T

(pu_0)

SDRAM Address Bit 10. Separate A10 signals enable SDRAM refresh operation while

the DSP executes non-SDRAM transactions.

SDCKE

I/O/T

(pu_m/

pd_m)

SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend

modes. A slave DSP in a multiprocessor system does not have the pull-up or pull-

down. A master DSP (or ID = 0 in a single processor system) has a pull-up before

granting the bus to the host, except when the SDRAM is put in self refresh mode. In

self refresh mode, the master has a pull-down before granting the bus to the host.

SDWE

I/O/T

(pu_0)

SDRAM Write Enable. When sampled low while CAS is active, SDWE indicates an

SDRAM write access. When sampled high while CAS is active, SDWE indicates an

SDRAM read access. In other SDRAM accesses, SDWE defines the type of operation to

execute according to SDRAM specification.

Table 9. Pin Definitions—JTAG Port

Signal

Type

Term

Description

EMU

O/OD

nc1

Emulation. Connected to the DSP’s JTAG emulator target board connector only.

TCK

epd or epu1

Test Clock (JTAG). Provides an asynchronous clock for JTAG scan.

TDI

I (pu_ad)

Test Data Input (JTAG). A serial data input of the scan path.

TDO

O/T

Test Data Output (JTAG). A serial data output of the scan path.

TMS

I (pu_ad)

Test Mode Select (JTAG). Used to control the test state machine.

TRST

I/A (pu_ad)

Test Reset (JTAG). Resets the test state machine. TRST must be asserted or pulsed low

after power-up for proper device operation. For more information, see Reset and

Booting on Page 9.

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal

pull-up 500

Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad

= internal pull-up 40 k

Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 22.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k

Ω to VSS; epu = external pull-up approx-

imately 5 k

Ω to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS

1 See the reference on Page 11 to the JTAG emulation technical reference EE-68.

Table 8. Pin Definitions—External Port SDRAM Controller (Continued)