参数资料
型号: ADSP21262SKBCZ200R
厂商: Analog Devices Inc
文件页数: 37/60页
文件大小: 0K
描述: IC DSP CTLR 32BIT 136CSPBGA
产品培训模块: SHARC Processor Overview
标准包装: 1
系列: SHARC®
类型: 定点/浮点
接口: DAI,SPI
时钟速率: 200MHz
非易失内存: ROM(512 kB)
芯片上RAM: 256kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 136-LFBGA,CSPBGA
供应商设备封装: 136-CSPBGA(12x12)
包装: 标准包装
其它名称: ADSP21262SKBCZ200RDKR
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and should
meet setup and hold times with regard to the serial clock on the
output port. The serial data output has a hold time and delay
Table 32. SRC, Serial Output Port
specification with regard to serial clock. Note that the serial
clock rising edge is the sampling edge and the falling edge is the
drive edge.
K and B Grade
Y Grade
Parameter
Min
Max
Max
Unit
Timing Requirements
t SRCSFS 1
t SRCHFS 1
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
3
3
ns
ns
Switching Characteristics
t SRCTDD 1
t SRCTDH 1
Transmit Data Delay After Serial Clock Falling Edge
Transmit Data Hold After Serial Clock Falling Edge
2
10.5
12.5
ns
ns
1
The data, serial clock, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be
either CLKIN or any of the DAI pins.
SAMPLE EDGE
t SRCCLK
DAI_P20–1
(SCLK)
t SRCCLKW
t SRCSFS
t SRCHFS
DAI_P20–1
(FS)
t SRCTDD
t SRCTDH
DAI_P20–1
(SDATA)
Figure 28. SRC Serial Output Port Timing
Rev. J |
Page 37 of 60 |
July 2013
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