参数资料
| 型号： | ADT7490ZEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 24/75页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADT7490 |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi |
| 标准包装： | 1 |
| 系列： | dBCool® |
| 类型： | 温度传感器 |
| 适用于相关产品： | ADT7490 |
| 所含物品： | 评估板 |
| 其它名称： | EVAL-ADT7490EBZ EVAL-ADT7490EBZ-ND |
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ADT7490
interrupt has cleared. Interrupt status register bits are sticky.
Whenever an interrupt status bit is set, indicating an
out-of-limit condition, it remains set even if the event that
caused it has gone away (until read).
The only way to clear the interrupt status bit is to read the
interrupt status register after the event has gone away.
Interrupt status mask registers allow individual interrupt
dedicated alert pin. However, if one of these masked
interrupt sources goes out of limit, its associated interrupt
status bit is set in the interrupt status registers.
Full details of the Interrupt Status and Interrupt Mask
registers associated with each measurement channels are
detailed in the Table 27 and in the full register map in the
Register Tables section.
sources to be masked from causing an SMBALERT on the
Table 27. INTERRUPT S TATUS AN D INTERRUPT MASK REGISTER ADDRESS AND BIT ASSIGNMENTS
Interrupt
Status
Interrupt
Mask
Register
0x41
0x42
0x43
0x81
Register
0x74
0x75
0x82
0x83
Bit 7
OOL
D2 FAULT
OOL
V TT
Bit 6
R2T
D1 FAULT
RES
I MON
Bit 5
LT
FAN4/THERM
RES
PECI3
Bit 4
R1T
FAN3
RES
PECI2
Bit 3
+5 V IN
FAN2
OVT
PECI1
Bit 2
V CC
FAN1
COM
M
RES
Bit 1
V CCP
OOL
DATA
RES
Bit 0
+2.5 V IN /THERM
+12 V IN
PECI0
RES
SMBALERT Interrupt Behavior
The ADT7490 can be polled for status, or an SMBALERT
interrupt can be generated for out-of-limit conditions. It is
important to note how the SMBALERT output and status
bits behave when writing interrupt handler software.
HIGH LIMIT
TEMPERATURE
4. Mask the interrupt source by setting the
appropriate mask bit in the interrupt mask registers
(0x74, 0x75, 0x82, and 0x83).
5. Take the appropriate action for a given interrupt
source.
6. Exit the interrupt handler.
7. Periodically poll the status registers. If the
interrupt status bit has cleared, reset the
corresponding interrupt mask bit to 0. This causes
the SMBALERT output and status bits to behave
“STICKY”
STATUS BIT
CLEARED ON READ
(TEMP BELOW LIMIT)
as shown in Figure 31.
Masking Interrupt Sources
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
SMBALERT
Figure 30. SMBALERT and Status Bit Behavior
Figure 30 shows how the SMBALERT output and sticky
status bits behave. Once a limit is exceeded, the
corresponding status bit is set to 1. The status bit remains set
until the error condition subsides and the status register is
read. The status bits are referred to as sticky, because they
remain set until read by software. This ensures that an
out-of-limit event cannot be missed if software is polling the
device periodically.
The interrupt mask registers allow individual interrupt
sources to be masked out to prevent SMBALERT interrupts.
Note that masking an interrupt source prevents only the
SMBALERT output from being asserted; the appropriate
status bit is set normally (see Figure 31). Full details of the
status and mask registers associated with each measurement
channel are detailed in Table 27 and Table 44.
HIGH LIMIT
TEMPERATURE
Note that the SMBALERT output remains low for the
entire duration that a reading is out of limit and until the
status register has been read. This has implications on how
software handles the interrupt.
“STICKY”
STATUS BIT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
CLEARED ON READ
(TEMP BELOW LIMIT)
Handling SMBALERT Interrupts
To prevent the system from being tied up servicing
interrupts, it is recommend to handle the SMBALERT
SMBALERT
INTERRUPT
MASK BIT SET
INTERRUPT MASK BIT
CLEARED
interrupt as follows:
1. Detect the SMBALERT assertion.
2. Enter the interrupt handler.
3. Read the status registers to identify the interrupt
(SMBALERT RE-ARMED)
Figure 31. How Masking the Interrupt Source Affects
SMBALERT Output
source.
http://onsemi.com
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