参数资料
| 型号： | ADT7490ZEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 49/75页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADT7490 |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi |
| 标准包装： | 1 |
| 系列： | dBCool® |
| 类型： | 温度传感器 |
| 适用于相关产品： | ADT7490 |
| 所含物品： | 评估板 |
| 其它名称： | EVAL-ADT7490EBZ EVAL-ADT7490EBZ-ND |
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ADT7490
Table 46. REGISTER 0x11 ? CONFIGURATION REGISTER 7 (POWER-ON DEFAULT = 0x00)
Bit No.
[0]
[1]
[2]
[3]
[4]
[7:5]
Mnemonic
THERMHys
FSPD
Vx1
FSPDIS
TODIS
RES
R/W (Note 1)
R/W
R/W
R/W
R/W
R/W
N/A
Description
THERM hysteresis is enabled by default. Setting this bit to 1 disables THERM hysteresis.
When set to 1, this bit runs all fans at maximum speed as programmed in the maximum PWM
duty cycle registers (0x38 to 0x3A). Power-on default = 0. This bit is not locked at any time.
BIOS should set this bit to 1 when the ADT7490 is configured to measure current from an
Analog Devices ADOPT VRM controller and to measure the CPU core voltage. This bit
allows monitoring software to display CPU watts usage. (Lockable.)
Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs go high for the
entire fan spin-up timeout selected.
When this bit is set to 1, the SMBus timeout feature is disabled. In this state, if at any point
during an SMBus transaction involving the ADT7490 activity ceases for more than 35 ms, the
ADT7490 assumes the bus is locked and releases the bus. This allows the ADT7490 to be
used with SMBus controllers that cannot handle SMBus timeouts. (Lockable.)
Reserved. Do not write to these bits.
1. This register becomes read-only when the Configuration Register 1 (0x40) Lock bit is set to 1. Any subsequent attempts to write to this
register fail.
Table 47. PECI READING REGISTERS (POWER-ON DEFAULT = 0x80)
Register Address
0x33
0x1A
0x1B
0x1C
R/W
Read-only
Read-only
Read-only
Read-only
Description
PECI0: This Register Reads the Eight Bits Representative of PECI Client Address 0x30
PECI1: This Register Reads the Eight Bits Representative of PECI Client Address 0x31
PECI2: This Register Reads the Eight Bits Representative of PECI Client Address 0x32
PECI3: This Register Reads the Eight Bits Representative of PECI Client Address 0x33
Table 48. I MON /V TT READING REGISTERS (POWER-ON DEFAULT = 0x00)
Register Address
0x1D
0x1E
R/W
Read-only
Read-only
Description
Reflects the voltage measurement at the I MON input on Pin 19 (8 MSBs of reading). Input
range of 0 V to 2.25 V.
Reflects the voltage measurement at the V TT input on Pin 8 (8 MSBs of reading). Input range
of 0 V to 2.25 V.
Table 49. REGISTER 0x1F ? EXTENDED RESOLUTION 3 (POWER-ON DEFAULT = 0x00)
Bit No.
[3:0]
[5:4]
[7:6]
R/W
Read-only
Read-only
Read-only
Description
Reserved
Hold the Two LSBs of the 10-bit V TT Measurement
Hold the Two LSBs of the 10-bit I MON Measurement
Table 50. VOLTAGE READING REGISTERS (POWER-ON DEFAULT = 0x00) (Note 1)
Register Address
0x20
0x21
0x22
0x23
0x24
R/W
Read-only
Read-only
Read-only
Read-only
Read-only
Description
Reflects the Voltage Measurement at the 2.5 V IN Input on Pin 22 (8 MSBs of Reading)
Reflects the Voltage Measurement (Note 2) at the V CCP Input on Pin 23 (8 MSBs of Reading)
Reflects the Voltage Measurement (Note 3) at the V CC Input on Pin 4 (8 MSBs of Reading)
Reflects the Voltage Measurement at the 5 V IN Input on Pin 20 (8 MSBs of Reading)
Reflects the Voltage Measurement at the 12 V IN Input on Pin 21 (8 MSBs of Reading)
1. If the extended resolution bits of these readings are also being read, the extended resolution registers (Register 0x76, Register 0x77) must
be read first. Once the extended resolution registers have been read, the associated MSB reading registers are frozen until read. Both the
extended resolution registers and the MSB registers are frozen.
2. If V CCP Low (Bit 6 of 0x10) is set, V CCP can control the sleep state of the ADT7490.
3. V CC (Pin 4) is the supply voltage for the ADT7490.
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