参数资料
| 型号： | ADT7490ZEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 51/75页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADT7490 |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi |
| 标准包装： | 1 |
| 系列： | dBCool® |
| 类型： | 温度传感器 |
| 适用于相关产品： | ADT7490 |
| 所含物品： | 评估板 |
| 其它名称： | EVAL-ADT7490EBZ EVAL-ADT7490EBZ-ND |
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ADT7490
Table 56. REGISTER 0x36 ? PECI CONFIGURATION REGISTER 1 (POWER-ON DEFAULT = 0x00)
Bit No.
[2:0]
Mnemonic
AVG[2:0]
R/W (Note 1)
R/W
Description
PECI Smoothing Interval. These bits set the duration over which smoothing is carried out on
the PECI data read. Note that the PECI smoothing interval is equal to the PECI register
update interval. The smoothing interval is calculated using the following formula:
Smooth Interval = #reads ? (t BIT ? 67 ? #CPU + t IDLE )
where:
#reads is the number of readings defined below.
t BIT is the negotiated bit rate.
67 is the number of bits in each PECI reading.
#CPU is the number of CPUs providing PECI data (1 to 4).
t IDLE = 14 m s, the delay between consecutive reads.
Bit Code
000
001
010
011
100
101
110
111
Number of PECI Readings
16
2048
4096
8192
16384
32768
65536
Reserved
[3]
[4]
[7:5]
DOM0
REPLACE
RES
R/W
R/W
R
CPU Domain Count information. Set to 0 indicates that CPU 1 associated with the PECI0
reading has a single domain (default). Set to 1 indicates that the system CPU 1 contains two
domains.
If this bit is set to 0, it indicates that the ADT7490 is operating in standard mode. If this bit is
set to 1, the Remote 1 Temperature register (Register 0x25) is overwritten by PECI0
information (Register 0x33) and vice versa. Note that in this mode, all associated user
programmable limit and fan control registers are also swapped and should be programmed in
the appropriate PECI or absolute temperature format.
Reserved
1. These registers become read-only when the Configuration Register 1 (0x40) Lock bit is set to 1. Any subsequent attempts to write to these
registers fail.
Table 57. MAXIMUM PWM DUTY CYCLE (POWER-ON DEFAULT = 0xFF) (Note 1)
Register Address
0x38
0x39
0x3A
R/W (Note 2)
R/W
R/W
R/W
Description
Maximum Duty Cycle for PWM1 Output, Default = 100% (0xFF)
Maximum Duty Cycle for PWM2 Output, Default = 100% (0xFF)
Maximum Duty Cycle for PWM3 Output, Default = 100% (0xFF)
1. These registers set the maximum PWM duty cycle of the PWM output.
2. These registers become read-only when the Configuration Register 1 (0x40) Lock bit is set to 1. Any subsequent attempts to write to these
registers fail.
Table 58. PECI T MIN REGISTER (POWER-ON DEFAULT = 0xE0, VALUE = ? 32)
Register Address
0x3B
R/W (Note 1)
R/W
Description
PECI T MIN . When the PECI measurement exceeds PECI T MIN , the appropriate fans run at
PWM MIN and increase according to the automatic fan speed control slope.
1. This register becomes read-only when the Configuration Register 1 (0x40) Lock bit is set. Any further attempts to write to this register have
no effect.
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