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| 型号： | ADUC7039BCP6Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 28/92页 |
| 文件大小： | 0K |
| 描述： | IC MCU ARM7 BATT SENSER 32LFCSP |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 连通性： | LIN，SPI |
| 外围设备： | POR，温度传感器，WDT |
| 输入/输出数： | 6 |
| 程序存储器容量： | 64KB（32K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 32 |
| 电压 - 电源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 数据转换器： | A/D 2x16b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 115°C |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 包装： | 托盘 |
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ADuC7039
Data Sheet
Rev. D | Page 34 of 92
ADC MMR INTERFACE
The ADC is controlled and configured through a number of
MMRs that are described in detail in the following sections.
All bits defined in the top eight MSBs (Bits[15:8]) of the ADCSTA
MMR are used as flags only and do not generate interrupts. All
bits defined in the lower eight LSBs (Bits[7:0]) of this MMR are
logic OR’ed to produce a single ADC interrupt to the MCU core. In
response to an ADC interrupt, user code should interrogate the
ADCSTA MMR to determine the source of the interrupt. Each
ADC interrupt source can be individually masked via the
ADCMSKI MMR described in the ADC Interrupt Mask
Register section.
All ADC result ready bits are cleared by a read of the ADC0DAT
MMR. If the current channel ADC is not enabled, all ADC result
ready bits are cleared by a read of the ADC1DAT MMR. To
ensure that I-ADC and V/T-ADC conversion data are syn-
chronous, user code should first read the ADC1DAT MMR
and then ADC0DAT MMR. New ADC conversion results are
not written to the ADCxDAT MMRs unless the respective ADC
result ready bits are first cleared. The only exception to this rule
is when the ARM core is powered down and the ADC subsystem
is active. In this mode, ADCxDAT registers always contain the
most recent ADC conversion result even though the ready bits
have not been cleared.
ADC Status Register
Name:
ADCSTA
Address:
0xFFFF0500
Default Value: 0x0000
Access:
Read only
Function:
This read-only register holds general status
information related to the mode of operation
or current status of the ADCs.
Table 27. ADCSTA MMR Bit Designations
Bit
Description
15
ADC calibration status.
This bit is set automatically in hardware to indicate an ADC calibration cycle has been completed.
This bit is cleared automatically after any of the following registers are written to: ADCMDE, ADCFLT, or ADC0CON.
14
Reserved.
13
ADC voltage/temperature conversion error.
This bit is set automatically in hardware to indicate that a voltage conversion overrange or underrange has occurred. The
conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case.
This bit is cleared automatically when a valid (in-range) voltage conversion result is written to the ADC1DAT register.
12
ADC current conversion error.
This bit is set automatically in hardware to indicate that a current conversion overrange or underrange has occurred. The
conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case.
This bit is cleared automatically when a valid (in-range) current conversion result is written to the ADC0DAT register.
11 to 6
Not used. These bits are reserved for future functionality and should not be monitored by user code.
5
ADC continuous interrupt bit.
This bit is set automatically after each I-ADC conversion. Results of the ADCs might not be valid. This bit is only active if enabled in
the ADCMDE MMR.
This bit is cleared when user code reads ADC0DAT.
4
Current channel ADC comparator threshold.
This bit is only valid if the current channel ADC comparator is enabled via the ADCCFG MMR.
This bit is set by hardware if the absolute value of the I-ADC conversion result exceeds the value written in the ADC0TH MMR.
This bit is cleared automatically by hardware when reconfiguring the ADC.
3
Reserved.
2
Temperature conversion result ready bit.
If the temperature channel ADC is enabled, this bit is set by hardware as soon as a valid temperature conversion result is written in
the temperature data register (ADC1DAT MMR). It is also set at the end of a calibration.
This bit is cleared when user code reads either ADC1DAT or ADC0DAT.
1
Voltage conversion result ready bit.
If the voltage channel ADC is enabled, this bit is set by hardware as soon as a valid voltage conversion result is written in the
voltage data register (ADC1DAT MMR). It is also set at the end of a calibration.
This bit is cleared when user code reads either ADC1DAT or ADC0DAT.
0
Current conversion result ready bit.
If the current channel ADC is enabled, this bit is set by hardware as soon as a valid current conversion result is written in the
current data register (ADC0DAT MMR). It is also set at the end of a calibration.
This bit is cleared when user code reads ADC0DAT.
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