参数资料
型号: ADUC814BRU
厂商: Analog Devices Inc
文件页数: 53/72页
文件大小: 0K
描述: IC ADC 12BIT W/FLASH MCU 28TSSOP
标准包装: 50
系列: MicroConverter® ADuC8xx
核心处理器: 8052
芯体尺寸: 8-位
速度: 16.78MHz
连通性: I²C,SPI,UART/USART
外围设备: POR,PSM,温度传感器,WDT
输入/输出数: 17
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
EEPROM 大小: 640 x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 6x12b; D/A 2x12b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
包装: 管件
配用: EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR
ADuC814
Rev. A | Page 57 of 72
INTERRUPT SYSTEM
The ADuC814 provides a total of twelve interrupt sources with two priority levels. The control and configuration of the interrupt system
is carried out through three interrupt-related SFRs.
IE
Interrupt Enable Register
IP
Interrupt Priority Register
IEIP2
Secondary Interrupt Enable and Priority Register
IE
Interrupt Enable Register
SFR Address
A8H
Power-On Default
00H
Bit Addressable
Yes
EA
EADC
ET2
ES
ET1
EX1
ET0
EX0
Table 29. IE SFR Bit Designations
Bit No.
Name
Description
7
EA
Global Interrupt Enable.
Set by the user to enable all interrupt sources.
Cleared by the user to disable all interrupt sources.
6
EADC
ADC Interrupt.
Set by the user to enable the ADC interrupt.
Cleared by the user to disable the ADC interrupt.
5
ET2
Timer 2 Interrupt.
Set by the user to enable the Timer 2 interrupt.
Cleared by the user to disable the Timer 2 interrupt.
4
ES
UART Serial Port Interrupt.
Set by the user to enable the UART serial port interrupt.
Cleared by the user to disable the UART serial port interrupt.
3
ET1
Timer 1 Interrupt.
Set by the user to enable the Timer 1 interrupt.
Cleared by the user to disable the Timer 1 interrupt.
2
EX1
INT1 Interrupt.
Set by the user to enable the External Interrupt 1.
Cleared by the user to disable the External Interrupt 1.
1
ET0
Timer 0 Interrupt.
Set by the user to enable the Timer 0 interrupt.
Cleared by the user to disable the Timer 0 interrupt.
0
EX0
INT0 Interrupt.
Set by the user to enable the External Interrupt 0.
Cleared by the user to disable the External Interrupt 0.
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