- 您现在的位置：买卖IC网 > PDF目录10937 > ADV202BBCZRL-115 (Analog Devices Inc)IC CODEC VIDEO 115MHZ 121CSPBGA PDF资料下载
参数资料
| 型号： | ADV202BBCZRL-115 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 21/40页 |
| 文件大小： | 0K |
| 描述： | IC CODEC VIDEO 115MHZ 121CSPBGA |
| 标准包装： | 1,500 |
| 类型： | JPEG2000 视频编解码器 |
| 分辨率（位）： | 16 b |
| 三角积分调变： | 无 |
| 电压 - 电源，模拟： | 1.5V，3.3V |
| 电压 - 电源，数字： | 1.5V，3.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 121-BGA，CSPBGA |
| 供应商设备封装： | 121-CSPBGA（12x12） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页当前第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页
ADV202
Data Sheet
Rev. D | Page 28 of 40
PIN CONFIGURATION AND BUS SIZES/MODES
The ADV202 provides a wide variety of control and data
configurations, which allows it to be used in many applications
with little or no glue logic. The following modes are configured
using the BUSMODE register. In the following descriptions,
host refers to normal addressed accesses (CS/RD/WR/ADDR)
and data refers to external DMA accesses (DREQ/DACK).
32-Bit Host/32-Bit Data
In this mode, the HDATA[31:0] pins provide full 32-bit wide data
accesses to PIXEL, CODE, and ATTR FIFOs. The expanded
video interface (VDATA) is not available in this mode.
16-Bit Host/32-Bit Data
This mode allows a 16-bit host to configure and communicate
with the ADV202 while still allowing 32-bit accesses to the
PIXEL, CODE, and ATTR FIFOs using the external DMA
capability.
All addressed host accesses are 16 bits and, therefore, use only
the HDATA[15:0] pins. The HDATA[31:16] pins provide the
additional 16 bits necessary to support the 32-bit external DMA
transfers to and from the FIFOs only. The expanded video
interface (VDATA) is not available in this mode.
16-Bit Host/16-Bit Data
This mode uses 16-bit transfers, if used for host or external
DMA data transfers. This mode allows for the use of the
extended pixel interface modes.
16-Bit Host/8-Bit Data (JDATA Bus Mode)
This mode provides separate data input/output and host
control interface pins. Host control accesses are 16 bits and use
HDATA[15:0], while the dedicated data bus uses JDATA[7:0].
JDATA uses a valid/hold synchronous transfer protocol. The
direction of the JDATA bus is determined by the mode of the
ADV202. If the ADV202 is encoding (compression), JDATA[7:0]
is an output. If the ADV202 is decoding (decompression),
JDATA[7:0] is an input. Host control accesses remain
asynchronous (also refer to the JDATA Mode section).
STAGE REGISTER
Because the ADV202 contains both 16-bit and 32-bit registers
and its internal memory is mapped as 32-bit data, a mechanism
has been provided to allow 16-bit hosts to access these registers
and memory locations using the stage register (STAGE).
STAGE is accessed as a 16-bit register using HDATA[15:0].
Prior to writing to the desired register, the stage register must be
written with the upper (most significant) half-word.
When the host subsequently writes the lower half-word to the
desired control register, HDATA is combined with the previously
staged value to create the required 32-bit value that is written.
When a register is read, the upper (most significant) half-word
is returned immediately on HDATA and the lower half-word
can be retrieved by reading the stage register on a subsequent
access. For details on using the stage register, see the ADV202
Note that the stage register does not apply to the three data
channels (PIXEL, CODE, and ATTR). These channels are
always accessed at the specified data width and do not require
the use of the stage register.
JDATA MODE
JDATA mode is typically used only when the dedicated video
interface (VDATA) is also enabled. This mode allows code
stream data (compressed data compliant with JPEG2000) to be
input or output on a single dedicated 8-bit bus (JDATA[7:0]).
The bus is always an output during compression operations
and is an input during decompression.
A 2-pin handshake is used to transfer data over this synchro-
nous interface. VALID is used to indicate that the ADV202 is
ready to provide or accept data and is always an output. HOLD
is always an input and is asserted by the host if it cannot accept/
provide data. For example, JDATA mode allows real-time
applications, in which pixel data is input over the VDATA bus
while the compressed data stream is output over the JDATA bus.
EXTERNAL DMA ENGINE
The external DMA interface is provided to enable high
bandwidth data I/O between an external DMA controller and
the ADV202 data FIFOs. Two independent DMA channels can
each be assigned to any one of the three data stream FIFOs
(PIXEL, CODE, or ATTR).
The controller supports asynchronous DMA using a data-
request/data-acknowledge (DREQ/DACK) protocol in either
single or burst access modes. Additional functionality is provided
for single address compatibility (fly-by) and dedicated chip
select (DCS) modes.
相关PDF资料 |
PDF描述 |
|---|---|
| VI-JNH-IX-S | CONVERTER MOD DC/DC 52V 75W |
| VI-JN4-IX-S | CONVERTER MOD DC/DC 48V 75W |
| AD1928YSTZ-RL | IC CODEC 2ADC 8DAC W/PLL 48LQFP |
| VI-JN2-IX-S | CONVERTER MOD DC/DC 15V 75W |
| VI-JN1-IX-S | CONVERTER MOD DC/DC 12V 75W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADV202BBCZRL-150 | 功能描述:IC CODEC VIDEO 150MHZ 144CSPBGA RoHS:是 类别:集成电路 (IC) >> 接口 - 编解码器 系列:- 标准包装:2,500 系列:- 类型:立体声音频 数据接口:串行 分辨率（位）:18 b ADC / DAC 数量:2 / 2 三角积分调变:是 S/N 比，标准 ADC / DAC (db):81.5 / 88 动态范围，标准 ADC / DAC (db):82 / 87.5 电压 - 电源，模拟:2.6 V ~ 3.3 V 电压 - 电源，数字:1.7 V ~ 3.3 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-WFQFN 裸露焊盘 供应商设备封装:48-TQFN-EP（7x7） 包装:带卷 (TR) |
| ADV202BCZ-150 | 制造商:Analog Devices 功能描述:JPEG 2000 CODEC CONVERTER, LEAD FREE - Trays |
| ADV202-HD-EB | 制造商:Analog Devices 功能描述: |
| ADV202-SD-EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD FOR ADV202 |
| ADV202XBBCZ-150 | 制造商:Analog Devices 功能描述:JPEG 2000 CODEC CONVERTER - Trays |
发布紧急采购，3分钟左右您将得到回复。