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参数资料
| 型号： | ADV3229ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/24页 |
| 文件大小： | 0K |
| 描述： | IC CROSSPOINT SW 16X8 72LFCSP |
| 标准包装： | 1 |
| 功能： | 交叉点开关 |
| 电路： | 1 x 8:8 |
| 电压电源： | 双电源 |
| 电压 - 电源，单路/双路(±)： | ±5V |
| 电流 - 电源： | 58mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 72-LFCSP-VQ（10x10） |
| 包装： | 托盘 |
ADV3228/ADV3229
Rev. 0 | Page 10 of 24
TRUTH TABLE AND LOGIC DIAGRAM
Table 8. Operation Truth Table1
CE
UPDATE
CLK
DATAIN
DATAOUT
RESET
SER/PAR
Description
1
X
No change in logic.
0
X
DataI2
DataI-80
X
0
The data on the serial DATAIN line is loaded into the
serial register. The first bit clocked into the serial
register appears at DATAOUT 40 clock cycles later.
0
X
0
D0…D3
Not applicable in
parallel mode3
X
1
The data on the parallel data lines, D0 to D3, are
loaded into the 40-bit serial shift register location
addressed at A0 to A2.
0
X
1
X
Data in the 40-bit shift register transfers into the
parallel latches that control the switch array. Latches
are transparent.
X
0
X
Asynchronous operation. All outputs are disabled.
Second rank latches are cleared. Remainder of logic
is unchanged.
1 X is don’t care.
2 DataI: serial data. Reserved bit internally set to Logic 1.
3 DATAOUT remains active in parallel mode and always reflects the state of the MSB of the serial shift register.
D
CLK
Q
3
T
O
8
D
E
CO
DE
R
A0
A1
A2
CLK
8
128
DATAIN
(SERIAL)
(OUTPUT
ENABLE)
SER/PAR
CE
UPDATE
OUT0 EN
DATA
OUT
PARALLEL
RESERVED
(INTERNALLY
SET HIGHT)
DATA
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
D1
D2
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
OUT1 EN
OUT2 EN
OUT3 EN
OUT4 EN
OUT5 EN
OUT6 EN
OUT7 EN
D
LE
Q
CLR
OUT7
EN
OUTPUT ENABLE
SWITCH MATRIX
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
D Q
CLK
S
D1
Q
D0
D3
DECODE
D
LE
Q
CLR
OUT0
EN
D
LE
OUT0
B0
Q
D
LE
Q
OUT0
B1
D
LE
Q
OUT0
B2
D
LE
Q
OUT0
R
D
LE
OUT1
B0
Q
D
LE
Q
CLR
OUT6
EN
D
LE
OUT7
B0
Q
D
LE
OUT7
B1
Q
D
LE
OUT7
B2
Q
D Q
CLK
S
D1
Q
D0
S
D1
Q
D0
D
LE
OUT7
R
Q
S
D1
Q
D0
OU
T
P
U
T
ADDRE
S
RESET
(OUTPUT ENABLE)
09
31
8-
0
06
Figure 6. Logic Diagram
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