参数资料
型号: ADV7194KSTZ
厂商: Analog Devices Inc
文件页数: 2/69页
文件大小: 0K
描述: IC ENCODER VIDEO EXT-10 80-LQFP
标准包装: 1
类型: 视频编码器
应用: DVD,视频,多媒体
电压 - 电源,模拟: 3.3 V ~ 5 V
电压 - 电源,数字: 3.3 V ~ 5 V
安装类型: 表面贴装
封装/外壳: 80-LQFP
供应商设备封装: 80-LQFP(14x14)
包装: 托盘
产品目录页面: 788 (CN2011-ZH PDF)
ADV7194
–10–
REV. A
PIN FUNCTION DESCRIPTIONS
Pin
Input/
No.
Mnemonic
Output
Function
1–10
P0–P9
I
10-Bit or 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port. The LSB of the input data is set up
on Pin P0 (Pin Number 1) in 10-bit input mode.
11–20
Y0/P10–Y9/P19
I
20-Bit or 16-Bit Multiplexed YCrCb Pixel Port or 1
× 10-bit progressive scan input for Y data.
21, 34, 68, 79
VDD
P
Digital Power Supply (3.3 V to 5 V).
22, 33, 43, 69,
DGND
G
Digital Ground.
80
23
HSYNC
I/O
HSYNC (Modes 1, 2, and 3) Control Signal. This pin may be congured to be an output
(Master Mode) or an input (Slave Mode) and accept Sync Signals.
24
VSYNC
I/O
VSYNC Control Signal. This pin may be congured as an output (Master Mode) or as an input
(Slave Mode) and accept
VSYNC as a Control Signal.
25
BLANK
I/O
Video Blanking Control Signal. This signal is optional. For further information see Verti-
cal Blanking and Data Insertion Blanking Input section.
26–31, 75–78
Cb0–Cb9
I
1
× 10-Bit Progressive Scan Input Port for Cb Data.
32
TTXREQ
O
Teletext Data Request Output Signal, used to control teletext data transfer.
35, 49, 52
AGND
G
Analog Ground.
36
CLKIN
I
TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alterna-
tively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.
37
CLKOUT
O
Clock Output Pin.
38, 48, 53
VAA
P
Analog Power Supply (3.3 V to 5 V).
39
SCL
I
MPU Port Serial Interface Clock Input.
40
SDA
I/O
MPU Port Serial Data Input/Output.
41
SCRESET/RTC/TR
I
Multifunctional Input: Real-Time Control (RTC) input, Timing Reset input, Subcarrier
Reset input.
42
ALSB
I
TTL Address Input. This signal sets up the LSB of the MPU address.
44
RSET2
I
A 1200
resistor connected from this pin to AGND is used to control full-scale amplitudes
of the Video Signals from the DAC D, E, F.
45
COMP 2
O
Compensation Pin for DACs D, E, and F. Connect a 0.1
F Capacitor from COMP 2 to
VAA.
46
DAC F
O
S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output.
47
DAC E
O
S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output.
50
DAC D
O
Composite/Y/Y/GREEN Analog Output. This DAC is capable of providing 4.33 mA output.
51
DAC C
O
S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output.
54
DAC B
O
S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output.
55
DAC A
O
Composite/Y/Y/GREEN Analog Output. This DAC is capable of providing 4.33 mA output.
56
COMP 1
O
Compensation Pin for DACs A, B, and C. Connect a 0.1
F Capacitor from COMP 1 to
VAA.
57
VREF
I/O
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). An external
VREF can not be used in 4
× oversampling mode.
58
RSET1
I
A 1200
resistor connected from this pin to AGND is used to control full-scale amplitudes
of the Video Signals from the DAC A, B, C.
59
PAL_NTSC
I
Input signal to select PAL or NTSC mode of operation, pin set to Logic 1 selects PAL.
60
RESET
I
The input resets the on-chip timing generator and sets the ADV7194 into default mode
See Appendix 8 for Default Register settings.
61
CSO_HSO
O
Dual function
CSO or HSO output Sync Signal at TTL level.
62
VSO/TTX/CLAMP
I/O
Multifunctional Pin.
VSO Output Sync Signal at TTL level. Teletext Data Input pin.
CLAMP TTL Output Signals can be used to drive external circuitry to enable clamping
of all Video Signals.
63–67, 70–74
Cr0–Cr9
I
1
× 10-Bit Progressive Scan Input Port for Cr Data.
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