
ADV7194
–30–
REV. A
MODE REGISTER 0
MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)
Figure 55 shows the various operations under the control of
Mode Register 0.
MR0 BIT DESCRIPTION
Output Video Standard Selection (MR00–MR01)
These bits are used to setup the encoder mode. The ADV7194
can be set up to output NTSC, PAL (B, D, G, H, I), or PAL N
standard video.
Luminance Filter Select (MR02–MR04)
These bits specify which luma lter is to be selected. The lter
selection is made independent of whether PAL or NTSC is
selected.
Chrominance Filter Select (MR05–MR07)
These bits select the chrominance lter. A low-pass lter can be
selected with a choice of cutoff frequencies (0.65 MHz, 1.0 MHz,
1.3 MHz, 2 MHz, or 3 MHz) along with a choice of CIF or
QCIF lters.
MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
Figure 56 shows the various operations under the control of
Mode Register 1.
MR1 BIT DESCRIPTION
DAC Control (MR10–MR15)
Bits MR15–MR10 can be used to power down the DACs. This are
used to reduce the power consumption of the ADV7194 or if any
of the DACs are not required in the application.
4
Oversampling Control (MR16)
To enable 4
× Oversampling this bit has to be set to 1. When
enabled, the data is output at a frequency of 54 MHz.
Note that PLL Enable Control has to be enabled (MR61 = 0) in
4
× Oversampling mode.
Reserved (MR17)
A Logical 0 must be written to this bit.
MR07
MR06
MR05
MR04
MR03
MR02
MR01
MR00
CHROMA FILTER SELECT
0
1.3 MHz LOW-PASS FILTER
0
1
0.65 MHz LOW-PASS FILTER
0
1
0
1.0 MHz LOW-PASS FILTER
0
1
2.0 MHz LOW-PASS FILTER
1
0
RESERVED
1
0
1
CIF
1
0
QCIF
1
3.0 MHz LOW-PASS FILTER
MR07 MR06 MR05
MR04 MR03 MR02
LUMA FILTER SELECT
0
LOW-PASS FILTER (NTSC)
0
1
LOW-PASS FILTER (PAL)
0
1
0
NOTCH FILTER (NTSC)
0
1
NOTCH FILTER (PAL)
1
0
EXTENDED MODE
1
0
1
CIF
1
0
QCIF
1
RESERVED
MR01 MR00
0
NTSC
0
1
PAL (B, D, G, H, I)
1
0
RESERVED
1
PAL (N)
OUTPUT VIDEO
STANDARD SELECTION
Figure 55. Mode Register 0, MR0
MR17
MR16
MR15
MR14
MR13
MR12
MR11
MR10
DAC A
DAC CONTROL
0
POWER-DOWN
1
NORMAL
MR15
DAC C
DAC CONTROL
0
POWER-DOWN
1
NORMAL
MR13
DAC E
DAC CONTROL
0
POWER-DOWN
1
NORMAL
MR11
4
OVERSAMPLING
CONTROL
02
OVERSAMPLING
14
OVERSAMPLING
MR16
DAC B
DAC CONTROL
0
POWER-DOWN
1
NORMAL
MR14
DAC D
DAC CONTROL
0
POWER-DOWN
1
NORMAL
MR12
DAC F
DAC CONTROL
0
POWER-DOWN
1
NORMAL
MR10
MR17
ZERO MUST
BE WRITTEN
TO THIS BIT
Figure 56. Mode Register 1, MR1