参数资料
| 型号： | ADV7194KSTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 46/69页 |
| 文件大小： | 0K |
| 描述： | IC ENCODER VIDEO EXT-10 80-LQFP |
| 标准包装： | 1 |
| 类型： | 视频编码器 |
| 应用： | DVD，视频，多媒体 |
| 电压 - 电源，模拟： | 3.3 V ~ 5 V |
| 电压 - 电源，数字： | 3.3 V ~ 5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-LQFP（14x14） |
| 包装： | 托盘 |
| 产品目录页面： | 788 (CN2011-ZH PDF) |
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ADV7194
–50–
REV. A
Time, tPD, is the time needed by the ADV7194 to interpolate
input data on TTX and insert it onto the CVBS or Y outputs,
such that it appears TSYNTTXOUT = 10.2
s after the leading edge of
the horizontal signal. Time TTXDEL is the pipeline delay time by
the source that is gated by the TTXREQ signal in order to deliver
TTX data.
With the programmability that is offered with TTXREQ signal
on the Rising/Falling edges, the TTX data is always inserted at
the correct position of 10.2
s after the leading edge of Horizontal
Sync pulse, thus this enables a source interface with variable
pipeline delays.
The width of the TTXREQ signal must always be maintained
such that it allows the insertion of 360 (in order to comply with
the Teletext Standard PAL-WST) teletext bits at a text data rate
of 6.9375 Mbits/s, this is achieved by setting TC03–TC00 to 0.
The insertion window is not open if the Teletext Enable bit
(MR33) is set to 0.
Teletext Protocol
The relationship between the TTX bit clock (6.9375 MHz) and
the system CLOCK (27 MHz) for 50 Hz is given as follows:
(27 MHz/4) = 6.75 MHz
(6.9375
× 106/6.75 × 106) = 1.027777
APPENDIX 5
TELETEXT INSERTION
Thus 37 TTX bits correspond to 144 clocks (27 MHz), each bit
has a width of almost four clock cycles. The ADV7194 uses
an internal sequencer and variable phase interpolation lter
to minimize the phase jitter and thus generate a bandlimited
signal which can be output on the CVBS and Y outputs.
At the TTX input the bit duration scheme repeats after every
37 TTX bits or 144 clock cycles. The protocol requires that
TTX Bits 10, 19, 28, 37 are carried by three clock cycles, all
other bits by four clock cycles. After 37 TTX bits, the next bits
with three clock cycles are Bits 47, 56, 65, and 74. This scheme
holds for all following cycles of 37 TTX bits, until all 360 TTX
bits are completed. All teletext lines are implemented in the
same way. Individual control of teletext lines are controlled
by Teletext Setup Registers.
ADDRESS & DATA
RUN-IN CLOCK
TELETEXT VBI LINE
45 BYTES (360 BITS) – PAL
Figure 98. Teletext VBI Line
PROGRAMMABLE PULSE EDGES
tPD
CVBS/Y
HSYNC
TTXREQ
TTXDATA
tSYNTTXOUT = 10.2 s
tPD = PIPELINE DELAY THROUGH ADV7194
TTXDEL = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
tSYNTTXOUT
10.2 s
TTXDEL
TTXST
Figure 99. Teletext Functionality Diagram
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADV7194KSTZ | 制造商:Analog Devices 功能描述:TV / Video IC |
| ADV7195 | 制造商:AD 制造商全称:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| ADV7195KS | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT VID+PROGSCAN/HDTV ENCODERIC - Bulk |
| ADV7195KST | 制造商:AD 制造商全称:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| ADV7195KSZ | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP |
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