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| 型号： | ADZS-21469-EZLITE |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/62页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL EZ LITE ADSP-21469 |
| 特色产品： | SHARC? 21469 EZ-KIT? and EZ-Board? for SHARC Processors |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | DSP |
| 适用于相关产品： | ADSP-2146x |
| 所含物品： | 板，线缆，调试程序，电源，软件 |
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Preliminary Technical Data
ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469
processors.
Table 2. Processor Benchmarks
Speed
FAMILY CORE ARCHITECTURE
The ADSP-2146x is code compatible at the assembly level with
the ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-21160, and
ADSP-21161, and with the first generation ADSP-2106x
SHARC processors. The ADSP-2146x shares architectural fea-
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, With Reversal)
FIR Filter (per Tap) 1
IIR Filter (per Biquad) 1
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]
Divide (y/×)
(at 450 MHz)
20.44 μ s
1.11 ns
4.43 ns
10.0 ns
17.78 ns
6.67 ns
tures with the ADSP-2126x, ADSP-2136x, ADSP-2137x, and
ADSP-2116x SIMD SHARC processors, as detailed in the fol-
lowing sections.
SIMD Computational Engine
The ADSP-2146x contains two computational processing ele-
ments that operate as a single-instruction, multiple-data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter, and reg-
1
Inverse Square Root
Assumes two files in multichannel SIMD mode
10.0 ns
ister file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
The ADSP-2146x continues SHARC’s industry-leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram on Page 1 illustrates the following architec-
tural features:
? Two processing elements, each of which comprises an
ALU, multiplier, shifter, and data register file
? Data address generators (DAG1, DAG2)
? Program sequencer with instruction cache
? PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
? Two programmable interval timers with external event
counter capabilities
? On-chip SRAM
? JTAG test access port
? FFT, FIR, IIR accelerators
The block diagram of the processor on Page 1 also illustrates the
following architectural features:
? DMA controller
? Digital applications interface that includes four precision
clock generators (PCG), an S/PDIF-compatible digital
audio receiver/transmitter with four independent asyn-
chronous sample rate converters, an input data port (IDP)
with eight serial ports, DTCP cipher, eight serial interfaces,
a 20-bit parallel input port (PDAP), and a flexible signal
routing unit (DAI SRU).
? Digital peripheral interface that includes two timers, one
UART, two serial peripheral interfaces (SPI), a 2-wire
interface (TWI), and a flexible signal routing unit
(DPI SRU).
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each pro-
cessing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the processor’s enhanced Harvard
architecture, allow unconstrained data flow between computa-
tion units and internal memory. The registers in PEX are
referred to as R0-R15 and in PEY as S0-S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-2146x features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 1 on page 1 ). With the its separate program and data
Rev. PrC
| Page 5 of 62 | January 2009
相关PDF资料 |
PDF描述 |
|---|---|
| ADZS-21479-EZLITE | KIT EVAL EZ BOARD ADSP-2147X |
| ADZS-21489-EZLITE | KIT EVAL EZ BOARD ADSP-2148X |
| ADZS-218X-ICE-2.5V | EMULATOR SRL FOR ADDS-218X-ICE |
| ADZS-BF506F-EZLITE | KIT EVAL EZLITE ADSP-BF506F |
| ADZS-BF518F-EZLITE | KIT EZ LITE BF512F/14F/16F/18F |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADZS-21479-EZBRD | 功能描述:BOARD EVAL FOR ADZS-2147X RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:SHARC® 标准包装:1 系列:PICDEM™ 类型:MCU 适用于相关产品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，线缆，元件，CD，PICkit 编程器 产品目录页面:659 (CN2011-ZH PDF) |
| ADZS-21479-EZBRD | 制造商:Analog Devices 功能描述:EZ BOARD SUPPORTING SHARC 21479 |
| ADZS-21479-EZLITE | 功能描述:KIT EVAL EZ BOARD ADSP-2147X RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:SHARC® 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| ADZS-21489-EZBRD | 功能描述:BOARD EVAL FOR ADZS-2148X RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:SHARC® 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| ADZS-21489-EZBRD | 制造商:Analog Devices 功能描述:EZ BOARD SUPPORTING SHARC 21489 |
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