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参数资料
| 型号： | AGL125-FFGG144 |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 125000 GATES, PBGA144 |
| 封装： | 13 X 13 MM, 1 MM PITCH, FBGA-144 |
| 文件页数： | 9/12页 |
| 文件大小： | 234K |
| 代理商： | AGL125-FFGG144 |
IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
6
Pr od uct Br ief
decryption engine and a Flash-based AES key that make
them the most comprehensive programmable logic
device security solution available today. IGLOO devices
with AES-based security allow for secure, remote field
updates over public networks such as the Internet, and
ensure that valuable IP remains out of the hands of
system overbuilders, system cloners, and IP thieves. The
contents of a programmed IGLOO device cannot be read
back, although secure design verification is possible.
Security, built into the FPGA fabric, is an inherent
component of the IGLOO family. The Flash cells are
located beneath seven metal layers, and many device
design and layout techniques have been used to make
invasive attacks extremely difficult. The IGLOO family,
with FlashLock and AES security, is unique in being highly
resistant to both invasive and noninvasive attacks. Your
valuable IP is protected and secure, making remote ISP
possible.
An
IGLOO
device
provides
the
most
impenetrable security for programmable logic designs.
Single Chip
Flash-based FPGAs store the configuration information
in
on-chip
Flash
cells.
Once
programmed,
the
configuration data is an inherent part of the FPGA
structure and no external configuration data needs to be
loaded at system power-up (unlike SRAM-based FPGAs).
Therefore, Flash-based IGLOO FPGAs do not require
system configuration components such as EEPROMs or
microcontrollers to load the device configuration data.
This reduces bill-of-materials costs and printed circuit
board (PCB) area, and increases security and system
reliability.
Live at Power-Up
The Actel Flash-based IGLOO devices support Level 0 of
the live at power-up (LAPU) classification standard. This
feature
helps
in
system
component
initialization,
execution of critical tasks before the processor wakes up,
setup and configuration of memory blocks, clock
generation, and bus activity management. The LAPU
feature of Flash-based IGLOO devices greatly simplifies
total system design and reduces total system cost, often
eliminating the need for complex programmable logic
devices (CPLDs) and clock generation PLLs that are used
for these purposes in a system. In addition, glitches and
brownouts in system power will not corrupt the IGLOO
device's Flash configuration, and unlike SRAM-based
FPGAs, the device will not have to be reloaded when
system power is restored. This enables the reduction or
complete removal of the configuration PROM, expensive
voltage
monitor,
brownout
detection,
and
clock
generator devices from the PCB design. Flash-based
IGLOO devices simplify total system design, and reduce
cost and design risk, while increasing system reliability
and improving system initialization time.
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost,
performance, and ease of use. Unlike SRAM-based
FPGAs, Flash-based IGLOO devices allow all functionality
to be live at power-up; no external boot PROM is
required. On-board security mechanisms prevent access
to all the programming information and enable secure
remote updates of the FPGA logic. Designers can
perform secure remote in-system reprogramming to
support future design iterations and field upgrades with
confidence that valuable intellectual property (IP) cannot
be compromised or copied. Secure ISP can be performed
using the industry-standard AES algorithm. The IGLOO
family device architecture mitigates the need for ASIC
migration at higher user volumes. This makes the IGLOO
family
a
cost-effective
ASIC
replacement
solution,
especially for applications in the consumer, networking/
communications, computing, and avionics markets.
Firm Errors
Firm errors occur most commonly when high-energy
neutrons, generated in the upper atmosphere, strike a
configuration cell of an SRAM FPGA. The energy of the
collision can change the state of the configuration cell
and thus change the logic, routing, or I/O behavior in an
unpredictable way. These errors are impossible to
prevent in SRAM FPGAs. The consequence of this type of
error can be a complete system failure. Firm errors do
not exist in the configuration memory of IGLOO Flash-
based FPGAs. Once it is programmed, the Flash cell
configuration element of IGLOO FPGAs cannot be
altered by high-energy neutrons and is therefore
immune to them. Recoverable (or soft) errors occur in
the user data SRAM of all FPGA devices. These can easily
be mitigated by using error detection and correction
(EDAC) circuitry built into the FPGA fabric.
Advanced Flash Technology
The IGLOO family offers many benefits, including
nonvolatility
and
reprogrammability
through
an
advanced Flash-based, 130-nm LVCMOS process with 7
layers of metal. Standard CMOS design techniques are
used to implement logic and control functions. The
combination of fine granularity, enhanced flexible
routing resources, and abundant Flash switches allows
for very high logic utilization without compromising
device routability or performance. Logic functions within
the device are interconnected through a four-level
routing hierarchy.
相关PDF资料 |
PDF描述 |
|---|---|
| AGL125-FG144I | FPGA, 125000 GATES, PBGA144 |
| AGL125-FG144 | FPGA, 125000 GATES, PBGA144 |
| AGL125-FGG144I | FPGA, 125000 GATES, PBGA144 |
| AGL125-FGG144 | FPGA, 125000 GATES, PBGA144 |
| AGL125-FQN132 | FPGA, 125000 GATES, QCC132 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AGL125V2-CS144 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL125V2-CS144ES | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL125V2-CS144I | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL125V2-CS144PP | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL125V2-CS196 | 功能描述:IC FPGA 1KB FLASH 125K 196-CSP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:IGLOO 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
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